Novel FPGA-Optimized Stochastic Number Generator for Stochastic Computing

Abstract

Stochastic computing (SC) is a computing domain that exploits probability mathematics to perform arithmetic operations with a single logic gate. The recent IoT and edge computing trends bring up the SC technology introduced in the 1960s due to its power efficiency and error resilience properties. In SC, a stochastic number generator (SNG) converts binary numbers into stochastic streams via a weighted binary generator (WBG) and linear feedback shift register (LFSR). Those application-specific integrated circuit (ASIC) logic gates might not be optimised for the field-programmable gate array (FPGA), causing FPGA resources underutilisation. In contrast, FPGA friendly multiplexer (MUX) could generate stochastic streams directly from binary input with a specialised finite state machine (FSM). However, it is limited on state tracking when the binary resolution expands, bottlenecking the MUX-based SNG's scalability. This paper proposes a novel function block of Weighed Binary Converter (WBC) to port the traditional LFSR to MUX, eliminating FSM bottlenecking and improving MUX SNG's scalability than WBG SNG in FPGA. The designs are synthesised with Xilinx Vivado HLS targeted at Z7010 FPGA SoC. The result shows that WBC enables 50% resource reduction on 4-bit MUX SNG and 62.5% bus width reduction on 8-bit MUX SNG, speeding up the logic setup time by 15.1% and 7.3%, respectively, compared to the ASIC logic transcoded WBG SNG.