Abstract
The phase frequency detector/charge pump is a significant source to raise the in-band phase noise of the phase-locked loop (PLL). The proposed CMOS-based pass transistor phase frequency detector (PT-PFD) solves the cycle skipping issue by improving the blind zone which in turn improves the phase noise performance. At the same time, in order to further improve the performance of the PLL, charge pump is integrated with the proposed design. In this case, the reset time has been reduced and thus the proposed PFD/CP functions up to the frequency of 1.5 MHz – 4.2 GHz. In addition, the modified pass transistor PFD architecture contains an advantage of less number of transistor count which consumes low power, i.e., 317.37 \(\mu W\). The design is based on standard 0.18 \(\mu m\) CMOS process technology with the supply voltage of 1.8 V. Moreover, the proposed design has completely eliminated the dead zone, and blind zone is minimized up to 44.23 ps which improves the phase noise to −133.8 dBc/Hz at 1 MHz offset frequency. The PFD/CP proposed herein just requires lower power consumption while producing less noise in charge pump phase-locked loop (CPLL) application.
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Notes
Charge sharing is the difference between the voltages that occurred due to two MOS switches.
Current mismatch is the difference between the charging/discharging current.
References
A. Abolhasani, M. Mousazadeh, A. Khoei, A high-speed, power efficient, dead-zone-less phase frequency detector with differential structure. Microelectron. J. 97, 104719 (2020)
P.V. Brennan, I. Thompson, Phase/frequency detector phase noise contribution in PLL frequency synthesiser. Electron. Lett. 37(15), 939–940 (2002)
C.T. Charles, D.J. Allstot, A calibrated phase/frequency detector for reference spur reduction in charge-pump PLLs. IEEE Trans. Circuits Syst. II 53(9), 822–826 (2006)
W.H. Chen, M.E. Inerowicz, B. Jung, Phase frequency detector with minimal blind zone for fast frequency acquisition. IEEE Trans. Circuits Syst. II 57(12), 936–940 (2010)
R.Y. Chen, Z.Y. Yang, S.C. Yu, High-frequency phase/frequency detectors: analysis for oscillation-free optimal I/O. IEEE Micro. Wireless Compon. Lett. 30(11), 1097–1100 (2020)
A. Fathi, M. Mousazadeh, A. Khoei, High-speed, low power, and dead zone improved phase frequency detector. IET Circuits Devices Syst. 13(7), 1056–1062 (2019)
X. Gao, E. Klumperink, M. Bohsali, B. Nauta, A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N\(^2\). IEEE J. Solid State Circuits 44(12), 3253–3263 (2009)
S.T. Ghasemi, A. Baradaranrezaeii, A novel high speed, low power, and symmetrical phase frequency detector with zero blind zone and \(\pi \) phase difference detection ability circuits. Syst. Signal Process. 39(6), 2880–2899 (2020)
H. Ghasemian, A. Bahrami, E. Abiri, M.R. Salehi, A new low-power charge pump with a glitch-free PFD for speedup the acquisition process of a PLL in 65 nm CMOS technology circuits. Syst. Signal Process. 40(6), 2982–3006 (2021)
M. Gholami, Phase detector with minimal blind zone and reset time for GSamples/s DLLs. Circuits Syst. Signal Process. 36(9), 3549–3563 (2017)
P.K. Hanumolu, M. Brownlee, K. Mayaram, U.K. Moon, Analysis of charge-pump phase-locked loops. IEEE Trans. Circuits Syst. I 51(9), 1665–1674 (2004)
A. Homayoun, B. Razavi, Analysis of phase noise in phase/frequency detectors. IEEE Trans. Circuits Syst. I 60(3), 529–539 (2013)
M.S. Hwang, J. Kim, D.K. Jeong, Reduction of pump current mismatch in charge-pump PLL. Electron. Lett. 45(3), 135–136 (2009)
A. Jakobsson, C. Grewing, A. Serban, S. Gong, Frequency synthesizer with dual loop frequency and gain calibration. IEEE Trans. Circuits Syst. I 60(11), 2911–2919 (2013)
T. Johnson, A. Fard, D. Aberg, An improved low voltage phase-frequency detector with extended frequency capability. The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS’04 51(9),1665-1674 (2004)
H.L. Kirankumar, S. Rekha, T. Laxminidhi, A dead-zone-free zero blind-zone high-speed phase frequency detector for charge-pump PLL. Circuits Syst. Signal Process (2020). https://doi.org/10.1007/s00034-020-01366-1
A. Koithyar, T.R. Kuppushetty, Integer-N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector. IET Circuits Devices Syst. 14(1), 60–65 (2020)
N. Kumar,M. Kumar, Design of low power and high speed phase detector. 2nd International Conference on Contemporary Computing and Informatics (IC3I),676-680 (2016)
J.S. Lee, M.S. Keel, S. Lim, S. Kim, Charge pump with perfect current matching characteristics in phase-locked loops. Electron. lett. 36(23), 1907–1908 (2000)
M. Mansuri, D. Liu, C.K.K. Yang, Fast frequency acquisition phase-frequency detectors for GSa/s phase-locked loops. IEEE J. Solid State Circuits 37(10), 1331–1334 (2002)
K.K.A. Majeed, K. Binsu, PLL architecture with a composite PFD and variable loop filter. IET Circuits Devices Syst. 12(3), 256–262 (2018)
U. Nanda, D.P. Acharya, D. Nayak, Process variation tolerant wide-band fast PLL with reduced phase noise using adaptive duty cycle control strategy. Int. J. Electron. 108(5), 705–717 (2021)
U. Nanda, D.P. Acharya, S.K. Patra, Design of an efficient phase frequency detector to reduce blind zone in a PLL. Springer Micros. Technol 23(3), 533–539 (2017)
N. Pradhan, S.K. Jana, Design of phase frequency detector with improved output characteristics operating in the range of 1.25 MHz-3.8 GHz. Analog Integr. Circuits Signal Process. 107(1), 101–108 (2021)
B. Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design (Wiley, Hoboken, 1996)
B. Razavi, Design of Analog CMOS Integrated Circuits (Tata McGraw-Hill Education, New York, 2001)
G.Y. Tak, S.B. Hyun, T.Y. Kang, B.G. Choi, S.S. Park, A 6.3–9-ghz cmos fast settling pll for MB-OFDM UWB applications. IEEE J. Solid State Circuits 40(8), 1671–1679 (2005)
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Authors would like to thank Ministry of Electronics and Information Technology (MeitY), Govt. of India, for providing financial support under SMDP-C2SD Project.
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Pradhan, N., Jana, S.K. Improved Phase Noise Performance of PFD/CP Operating in 1.5 MHz– 4.2 GHz for Phase-Locked Loop Application. Circuits Syst Signal Process 41, 6651–6671 (2022). https://doi.org/10.1007/s00034-022-02117-0
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DOI: https://doi.org/10.1007/s00034-022-02117-0