Skip to main content
SpringerLink
Log in

A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation (\(F_{\max }\)) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 \(\upmu \)W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 \(\upmu {\text {m}}^2\).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16

Similar content being viewed by others

References

  1. R.E. Best, Phase Locked Loops: Design, Simulation, and Applications (McGraw-Hill Professional, New York, 2007)

    Google Scholar 

  2. W.H. Chen, M.E. Inerowicz, B. Jung, Phase frequency detector with minimal blind zone for fast frequency acquisition. IEEE Trans. Circuits Syst. II: Express Briefs 57(12), 936–940 (2010)

    Article  Google Scholar 

  3. F.M. Gardner, Phaselock Techniques (Wiley, New York, 2005)

    Book  Google Scholar 

  4. M. Gholami, Phase detector with minimal blind zone and reset time for GSamples/s DLLs. Circuits Syst. Signal Process. 36(9), 3549–3563 (2017)

    Article  Google Scholar 

  5. Y. He , X. Cui , C.L. Lee , D. Xue, An improved fast acquisition PFD with zero blind zone for the PLL application, in 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, pp. 1–2 (2014). https://doi.org/10.1109/EDSSC.2014.7061226

  6. S.S. Kuncham, M. Gadiyar, K. Sushmitha Din, K.K. Lad, T. Laxminidhi, A novel zero blind zone phase frequency detector for fast acquisition in phase locked loops, in 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), pp. 167–170 (2018).https://doi.org/10.1109/VLSID.2018.56

  7. K.K.A. Majeed, B.J. Kailath, Analysis and design of low power nonlinear PFD architectures for a fast locking PLL, in 2016 IEEE Students’ Technology Symposium, pp. 136–140 (2016).https://doi.org/10.1109/TechSym.2016.7872670

  8. J.M. Rabaey, A.P. Chandrakasan, B. Nikolic, Digital Integrated Circuits (Prentice Hall, Englewood Cliffs, 2002)

    Google Scholar 

  9. B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd edn. (McGraw-Hill, New Delhi, 2017)

    Google Scholar 

  10. A. Rezaeian, G. Ardeshir, M . Gholami, A low-power and high-frequency phase frequency detector for a 3.33-GHz delay locked loop. Circuits, Syst. Signal Process. pp. 1–16 (2019)

  11. C.A. Sharpe, A 3-state phase detector can improve your next PLL design. EDN 20, 55–59 (1976)

    Google Scholar 

  12. S. Sofimowloodi, F. Razaghian, M. Gholami, Low-power high-frequency phase frequency detector for minimal blind-zone phase-locked loops. Circuits Syst. Signal Process. 38(2), 498–511 (2019)

    Article  Google Scholar 

  13. S. Soliman, F. Yuan, K. Raahemifar, An overview of design techniques for CMOS phase detectors, in 2002 IEEE International Symposium on Circuits and Systems vol. 5, pp. 457–460 (2002). https://doi.org/10.1109/ISCAS.2002.1010739

  14. M. Soyuer, R.G. Meyer, Frequency limitations of a conventional phase-frequency detector. IEEE J. Solid-State Circuits 25(4), 1019–1022 (1990)

    Article  Google Scholar 

  15. Z. Zahir, G. Banerjee, A fast acquisition phase frequency detector for high frequency PLLs, in 2015 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE), pp. 366–369 (2015)

Download references

Acknowledgements

The authors would like to thank The Ministry of Electronics and Information Technology(MeitY), Government of India for the necessary tool support provided to carry out this work under SMDP-C2SD Project.

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Karnataka, Surathkal, 575025, India

    H. Lad Kirankumar, S. Rekha & Tonse Laxminidhi

Authors
  1. H. Lad Kirankumar
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. S. Rekha
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Tonse Laxminidhi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to H. Lad Kirankumar.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Lad Kirankumar, H., Rekha, S. & Laxminidhi, T. A Dead-Zone-Free Zero Blind-Zone High-Speed Phase Frequency Detector for Charge-Pump PLL. Circuits Syst Signal Process 39, 3819–3832 (2020). https://doi.org/10.1007/s00034-020-01366-1

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-020-01366-1

Keywords

Search

Navigation