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High-Speed and Area-Efficient CMOS and CNFET-Based Level-Shifters

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Abstract

This paper proposes CMOS- and Carbon Nanotube FET (CNFET)-based high-speed level-shifter circuits. The proposed level-shifter designs make use of the Low-Threshold-Voltage Transistors and High-Threshold-Voltage Transistors devices available in the CNFET and 45 nm CMOS technologies, to significantly reduce the propagation delays and transistor count. The performance of the proposed level-shifters has been compared with the conventional level-shifter and other state-of-the-art level-shifter designs reported in the literature. The proposed level-shifters operate significantly faster (98% lower prorogation delays) as compared to the benchmarked level-shifter designs, and a reduction of 95% in Power Delay Product can be achieved.

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References

  1. B. Calhoun, J. Kao, A. Chandrakasan, Power Gating and Dynamic Voltage Scaling (Springer US, Boston, MA, 2006), pp. 41–75. https://doi.org/10.1007/0-387-28133-9_3

  2. X. Chen, N.A. Touba, in Electronic Design Automation, ed. by L.T. Wang, Y.W. Chang, K.T.T. Cheng (Morgan Kaufmann, Boston, 2009), pp. 39–95. https://doi.org/10.1016/B978-0-12-374364-0.50009-6

  3. H.S.P. Deng, Wong, Electron Devices. IEEE Transactions on 54, 3195 (2007)

    Article  Google Scholar 

  4. J. Deng, H.P. Wong, IEEE Transactions on Electron Devices 54(12) (2007). https://doi.org/10.1109/TED.2007.909030

  5. A.K. Gupta, R. Johari, in 2019 4th International Conference on Internet of Things: Smart Innovation and Usages (IoT-SIU) (2019), pp. 1–5. https://doi.org/10.1109/IoT-SIU.2019.8777342

  6. D. Gupta, V. Hugo, A. Khanna, P.L. Mehta, Smart Sensors for Industrial Internet of Things (Springer, Boston, MA, 2021). https://doi.org/10.1007/978-3-030-52624-5

  7. O. Hashemipour, M.H. Moaiyeri, R.F. Mirzaee, A. Doostaregan, K. Navi, IET Computers & Digital Techniques 7(4), 167 (2013). https://doi.org/10.1049/iet-cdt.2013.0023

    Article  Google Scholar 

  8. IEEE Transactions on Circuits and Systems II, Express Briefs 61(10), 753 (2014). https://doi.org/10.1109/TCSII.2014.2345295

    Article  Google Scholar 

  9. S. Kabirpour, M. Jalali, IEEE Transactions on Circuits and Systems II: Express Briefs 66(6), 909 (2019). https://doi.org/10.1109/TCSII.2018.2872814

    Article  Google Scholar 

  10. M. Lanuzza, P. Corsonello, S. Perri, IEEE Transactions on Circuits and Systems II: Express Briefs 59(12), 922 (2012). https://doi.org/10.1109/TCSII.2012.2231037

    Article  Google Scholar 

  11. M. Lanuzza, P. Corsonello, S. Perri, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23(2), 388 (2015). https://doi.org/10.1109/TVLSI.2014.2308400

  12. A. Ltd. Microprocessor cores and technology arm. https://www.arm.com/products/silicon-ip-cpu

  13. P.O. Pouliquen, in Proceedings of 2010 IEEE International Symposium on Circuits and Systems (2010), pp. 4097–4100. https://doi.org/10.1109/ISCAS.2010.5537627

  14. J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, second, edition. (Pearson Education India, S.l., 2016)

    Google Scholar 

  15. Resource & Design Center for Development with Intel. https://www.intel.com/content/www/us/en/design/resource-design-center.html

  16. D. Sehrawat, N.S. Gill, in 2019 3rd International Conference on Trends in Electronics and Informatics (ICOEI) (2019), pp. 523–528. https://doi.org/10.1109/ICOEI.2019.8862778

  17. S.M. Sharroush, Ain Shams Engineering Journal 9(4), 1001 (2018). https://doi.org/10.1016/j.asej.2016.05.005

    Article  Google Scholar 

  18. T. Simunic, L. Benini, A. Acquaviva, P. Glynn, G. De Micheli, (Association for Computing Machinery, New York, NY. USA (2001). https://doi.org/10.1145/378239.379016

    Article  Google Scholar 

  19. Y. Taur, T.H. Ning, Fundamentals of Modern VLSI Devices, 2nd edn. (Cambridge, Place of publication not identified, 2004). OCLC: 316331820

  20. F. Wu, T. Wu, M.R. Yuce, in 2019 IEEE 5th World Forum on Internet of Things (WF-IoT) (2019), pp. 87–90. https://doi.org/10.1109/WF-IoT.2019.8767280

  21. C. Xian, Y.H. Lu, Z. Li, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(8), 1467 (2008). https://doi.org/10.1109/TCAD.2008.925778

    Article  MathSciNet  Google Scholar 

  22. S.H. Yang, C.C. Chiu, C.W. Chang, C.M. Chen, C.H. Meng, K.H. Chen, IEEE Transactions on Power Electronics 31(4), 3118 (2016). https://doi.org/10.1109/TPEL.2015.2450746

    Article  Google Scholar 

  23. D. Zhao, T. Bakhishev, L. Scudder, P.E. Gregory, M. Duane, U.C. Sridharan, P. Ranade, L. Shifren, T. Hoffmann. Semiconductor structure with multiple transistors having various threshold voltages (2017). https://patents.google.com/patent/US9812550B2/en

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Authors and Affiliations

  1. Department of ECE, Mahindra University École Centrale School of Engineering, Hyderabad, Telangana, 500043, India

    Abhay S. Vidhyadharan

  2. Department of Electronics and Electrical Engineering, Birla Institute of Technology and Science Pilani, Hyderabad Campus, Telangana, 500078, India

    Aiswarya Satheesh, Kilari Pragnaa & Sanjay Vidhyadharan

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  1. Abhay S. Vidhyadharan
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Vidhyadharan, A.S., Satheesh, A., Pragnaa, K. et al. High-Speed and Area-Efficient CMOS and CNFET-Based Level-Shifters. Circuits Syst Signal Process 41, 4649–4670 (2022). https://doi.org/10.1007/s00034-022-01999-4

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