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A 100MHz, 5.6pJ EPT, 1V to 15V full swing level shifter using low voltage transistors

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Abstract

This paper presents a fast and power-efficient high voltage level shifter architecture capable of converting low level of input voltages into extremely high output voltage levels. The presented architecture uses single type of PMOS and NMOS transistors, operated at three times the safe operating area limit of transistors. The circuit is designed to take an input signal of 1V/0 and provides multiple output signals varying between 15, 10 and 5V/0 under the specified load condition. Circuit is designed and implemented in 110nm-BCD technology using 5V capable transistors. Post-layout simulation results demonstrate a total Energy Per Transition of 5.6pJ, a static current consumption of 180pA, and a propagation delay of 2nS for an input frequency of 100MHz.

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Authors and Affiliations

  1. STMicroelectronics Pvt Ltd, Greater Noida, India

    Vikas Rana & Arpit Vijayvergia

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  1. Vikas Rana
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  2. Arpit Vijayvergia
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Correspondence to Vikas Rana.

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Rana, V., Vijayvergia, A. A 100MHz, 5.6pJ EPT, 1V to 15V full swing level shifter using low voltage transistors. Analog Integr Circ Sig Process 111, 243–250 (2022). https://doi.org/10.1007/s10470-021-01932-w

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  • DOI: https://doi.org/10.1007/s10470-021-01932-w

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