High-Accuracy Time-Mode Duty-Cycle-Modulation-Based Temperature Sensor for Energy-Efficient System Applications

Abstract

This paper presents a new time-mode duty-cycle-modulation-based high-accuracy temperature sensor. Different from the well-known ${\varSigma }{\varDelta }$ ADC-based readout structure, this temperature sensor utilizes a temperature-dependent oscillator to convert the temperature information into temperature-related time-mode parameter values. The useful output information of the oscillator is the duty cycle, not the absolute frequency. In this way, this time-mode duty-cycle-modulation-based temperature sensor has superior performance over the conventional inverter-chain-based time domain types. With a linear formula, the duty-cycle output streams can be converted into temperature values. The design is verified in 65nm standard digital CMOS process. The verification results show that the worst temperature inaccuracy is kept within 1$\,^{\circ }\mathrm{C}$ with a one-point calibration from $-$55 to 125 $^{\circ }\mathrm{C}$. At room temperature, the average current consumption is only 0.8 $\upmu$A (1.1$\,\upmu$A in one phase and 0.5 $\upmu$A in the other) with 1.2 V supply voltage, and the total energy consumption for a complete measurement is only 0.384 ${\hbox {nJ}}$.

Appendices

Appendix 1: Proof of Choosing NMOS Transistors for PTAT Current Generator

Although bipolar transistors have better linearity than MOS transistors in subthreshold region, there are two reasons for the utilizing of MOS transistors in this design.

The first consideration is the proper operation of the PMOS current source transistors. As the supply voltage is only 1.2V and the threshold voltages of the transistors are approximated to 0.5 V, the value of $V_{NS}$ is around 0.5 V in room temperature. If bipolar transistors are adopted, $V_{NS}$ becomes greater than 0.6 V in room temperature, which will drive the current source transistors into triode region. The accuracy of current mirroring will be affected.

On the other hand, the performance of parasitic bipolar transistors (PNPs) is not excellent in deep submicron processes. Based on simulations of the PNPs, the current gain $\beta$ (current ratio of $I_C$ over $I_B$) is even less than 1, which means the base current becomes comparable to the collector current.

As in most calculations, the base current is ignored based on large $\beta$ value and the emitter current is supposed to be equal to the collector current. However, due to small $\beta$ values, the errors of $V_{BE}$ caused by $\beta$s cannot be neglected in the design.

$$\begin{aligned} V_{BE1}= & {} \frac{kT}{q}ln\left( \frac{I_{C1}}{I_{S1}}\right) =\frac{kT}{q}ln\left( \frac{I_{\text {PTAT}}}{I_{S1}}\frac{\beta _1}{\beta _1+1}\right) \end{aligned}$$

(10)

$$\begin{aligned} V_{BE2}= & {} \frac{kT}{q}ln\left( \frac{I_{C2}}{I_{S2}}\right) =\frac{kT}{q}ln\left( \frac{I_{\text {PTAT}}}{I_{S2}}\frac{\beta _2}{\beta _2+1}\right) \end{aligned}$$

(11)

$$\begin{aligned} {\varDelta }V_{BE}= & {} V_{BE1}-V_{BE2} =\frac{kT}{q}ln\left( \frac{I_{S1}}{I_{S2}}\frac{\beta _1}{\beta _1+1}\frac{\beta _2+1}{\beta _2}\right) \end{aligned}$$

(12)

$$\begin{aligned} I_{\text {PTAT}}= & {} \frac{{\varDelta }V_{BE}}{R_b} =\frac{\left( V_{BE1}-V_{BE2}\right) }{R_b} =\frac{kT}{q\cdot R_b}ln\left( \frac{I_{S1}}{I_{S2}}\frac{\beta _1}{\beta _1+1}\frac{\beta _2+1}{\beta _2}\right) \end{aligned}$$

(13)

In Eqs. (10–14), two bipolar transistors $Q_1$ and $Q_2$ are biased equally by $I_{\text {PTAT}}$. Each one has a saturation current $I_S$ and current gain $\beta$ accordingly. The bias current is generated by ${\varDelta }V_{BE}$ crossing resistor $R_b$. As shown in Eq. (13), the final PTAT current includes the parameter $\beta$. Unfortunately, $\beta _1$ and $\beta _2$ are not equal. Therefore, significant error appears with difference of $\beta$s .

Additionally, the value of $\beta$s is not flat when the emitter currents are swept. It is better to bias the PNPs with at least 1 $\upmu A$ currents for operation in the flat region. Such large biasing current is not reasonable in the proposed application. Therefore, NMOS transistors instead of PNPs are chosen in the design.

Appendix 2: Evaluation of the Influence of Mismatches

(1) Mismatch of Capacitors

For a10 $\upmu$m x10 $\,\upmu$m MIM capacitor, ${\varDelta }$C/C is approximated to 0.01 % according to the tech files provided by the foundry. In the proposed design, 6pF for C1 and C2 is chosen (reasons will be calculated in the following answer) and the capacitor’s mismatch is $100/2500\times 0.01\,\%\,=\,4\times 10^{-6}$.

Employing Eq. (5):

$$\begin{aligned} \upmu = \frac{{n \cdot {\varDelta }{V_{BE}}}}{{{V_{BE}} + n \cdot {\varDelta }{V_{BE}}}} = \frac{{\frac{{{I_1} \cdot {t_1}}}{{{C_1}}}}}{{\frac{{{I_3} \cdot {t_3}}}{{{C_3}}} + \frac{{{I_1} \cdot {t_1}}}{{{C_1}}}}} = \frac{{{t_1}}}{{{t_3} + {t_1}}} \end{aligned}$$

(14)

Considering the mismatch between $C_1$ and $C_3$, assume $C_3$ =  (1+${\varDelta }$C/C)$C_1$, the above equation becomes:

$$\begin{aligned} \begin{aligned} {\upmu = {{{{{I_1} \cdot {t_1}} \over {{C_1}}}} \over {{{{I_3} \cdot {t_3}} \over {{C_3}}} + {{{I_1} \cdot {t_1}} \over {{C_1}}}}} = {{{t_1}} \over {{t_1} + {t_3}{1 \over {1 + {\varDelta }C/C}}}} \approx {{{t_1}} \over {{t_1} + {t_3}\left( 1 - {{{\varDelta }C} \over C}\right) }} = {{{t_1}} \over {{t_1} + {t_3} - {t_3}{{{\varDelta }C} \over C}}}} \\{ = {{{t_1}} \over {\left( {t_1} + {t_3}\right) \left( 1 - {{{t_3}} \over {{t_1} + {t_3}}}{{{\varDelta }C} \over C}\right) }} = {{{t_1}} \over {{t_1} + {t_3}}}\left( 1 + {{{t_3}} \over {{t_1} + {t_3}}}{{{\varDelta }C} \over C}\right) } \\\end{aligned} \end{aligned}$$

(15)

As the values of duty cycle are within 0.4 to 0.7 in the proposed design, the same range can be applied to $t_1/(t_1+t_3 )$. Therefore, the mismatch caused $\upmu$ error (duty-cycle error) is less than $0.7\times 4\times 10^{-6}$. When the duty-cycle error is converted into actual temperature error, it is less than $2.8\times 10^{-6}\times 600 \,$ = 1.68m$\,^{\circ }$C, which can be ignored in the proposed application.

(2) Mismatch of Currents

Using the same analysis for the mismatch of capacitors, assume $I_3=(1+{\varDelta }I/I_1) I_1$, Eq. (5) becomes:

$$\begin{aligned} \begin{aligned}&{\upmu = {{{{{I_1} \cdot {t_1}} \over {{C_1}}}} \over {{{{I_3} \cdot {t_3}} \over {{C_3}}} + {{{I_1} \cdot {t_1}} \over {{C_1}}}}} = {{{t_1}} \over {{t_1} + {t_3}\left( 1 + {{{\varDelta }I} \over I}\right) }} = {{{t_1}} \over {{t_1} + {t_3} + {t_3}{{{\varDelta }I} \over I}}}} \\&{ = {{{t_1}} \over {\left( {t_1} + {t_3}\right) \left( 1 + {{{t_3}} \over {{t_1} + {t_3}}}{{{\varDelta }I} \over I}\right) }} = {{{t_1}} \over {{t_1} + {t_3}}}\left( 1 + {{{t_3}} \over {{t_1} + {t_3}}}{{{\varDelta }I} \over I}\right) } \end{aligned} \end{aligned}$$

(16)

With the adopted DEM technique (just 3 more pairs of switches, negligible area), the residue mismatch reduces from $t_3/(t_1+t_3 ){\varDelta }I/I$ to $t_3/(t_1+t_3 )({\varDelta }I/I)^2$. With a usual current mirror inaccuracy of 1 %, the residue is less than $0.7\times (1\,\%)^2= 7\times 10^{-5}$ .

Related calculation can be found in page 60 of [10].

When it is converted into temperature error, it will be $7\times 10^{-5}\times 600$ = 0.04$\,^{\circ }$C, which can be ignored in the proposed application.