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An Offset Compensated Sampled-Data CMOS Comparator Circuit for Low-Power Implantable Biosensor Applications

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Abstract

This paper proposes a new low-voltage high resolution complementary metal oxide semiconductor (CMOS) comparator circuit suitable for biosensor applications. The comparator compensates for differential input offset through single-ended sampled-data preamplification. Simulations were carried out using a 130 nm IBM CMOS (CMRF8SF) process technology. Monte Carlo simulations incorporating mismatch between devices (based on width and length of devices) indicate that the design is quite robust. The comparator has a differential input overdrive resolution of under 1 mV and a response time which is scalable. The capacity for offset compensation trades with the bandwidth of the comparator through the size of the device channel areas (Width × Length) of the transistors. The static micropower consumed by the comparator from a 0.5 V supply voltage is under 10 μW, making it extremely suitable for miniaturized implantable biosensor devices. In addition, the comparator uses a single clock scheme for the sampled-data operations, which eliminates the need for special clock generation circuitry.

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  1. Center for Research in Analog & VLSI Microsystem dEsign (CRAVE), Institute of Technology and Engineering (ITE), Massey University, Room: 106.20B, BUILDING 106, Gate 4, Albany, Auckland, 1311, New Zealand

    S. M. Rezaul Hasan

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  1. S. M. Rezaul Hasan
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Correspondence to S. M. Rezaul Hasan.

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Rezaul Hasan, S.M. An Offset Compensated Sampled-Data CMOS Comparator Circuit for Low-Power Implantable Biosensor Applications. Circuits Syst Signal Process 27, 351–366 (2008). https://doi.org/10.1007/s00034-008-9031-1

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  • DOI: https://doi.org/10.1007/s00034-008-9031-1

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