Abstract
If off-line testing is complemented by on-line checks, in general some of the test hardware is only used either for on-line checking (e.g., control flow monitors) or for production testing (e.g., pattern generators). In this article a hardware structure for controllers is presented, in which the complete test circuitry can be used for both facilitating a self-test and for checking the control flow during normal operation. The corresponding design procedure considers this target structure while synthesizing the controller from a behavioral description and thus minimizes the hardware overhead. Existing approaches for designing concurrently checked controllers can be represented as special cases in the formal framework established in this article.
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F. Brglez, D. Bryan, J. Calhoun, G. Kedem, R. Lisanke, “Automated Synthesis for Testability,”IEEE Trans. on Industrial Electronics, vol. 36, pp. 263–277, 1989.
S. Devadas, H.T. Ma, A.R. Newton, “Redundancies and don't cares in sequential logic synthesis,”Journal of Electronic Testing: Theory and Applications, vol. 1, pp. 15–30, 1990.
S. Devadas, H.T. Ma, A.R. Newton, A. Sangiovanni-Vincentelli, “Optimal logic synthesis and testability: Two faces of the same coin,”Proc. Int. Test Conf. pp. 4–12, 1988.
G. Hachtel, R. Jacoby, K. Keutzer, C. Morrison, “On properties of algebraic transformations and the multifault testability of multilevel logic,”Proc. Int. Conf. on Computer-Aided Design, pp. 418–421, 1989.
P. Camurati, P. Prinetto, “Formal verification of hardware correctness: An introduction,”Computer Hardware Description Languages and their Applications, North Holland: Elsevier, 1987.
T. Kropf, H.-J. Wunderlich, “A common approach to test generation and hardware verification based on temporal logic,”Proc. Int. Test Conf., pp. 57–66, 1991.
M. Nicolaidis, “Self-exercising checkers for unified built-in self-test(UBIST),”IEEE Trans. on Computer-Aided Design, vol. 8, pp. 203–218, 1989.
M. Namjoo, “Techniques for concurrent testing of VLSI processor operation,Proc. Int. Test Conf., pp. 461–468, 1982.
T. Sridhar, S.M. Thatte, “Concurrent checking of program flow in VLSI processors,”Proc. Int. Test Conf., pp. 191–199, 1982.
K.D. Wilken, “Optimal signature placement for processor-error detection using signature monitoring,”Dig. 21st Int. Symp. Fault-Tolerant Computing, pp. 326–333, 1991.
R. Leveugle, G. Saucier, “Optimized synthesis of concurrently checked controllers,”IEEE Trans. on Computers, vol. C-39, pp. 419–425, 1990.
S.H. Robinson, J.P. Shen, “Evaluation and Synthesis of Self-Monitoring State Machines,”Proc. Int. Conf. on Computer-Aided Design, pp. 276–279, 1990.
B. Könemann, J. Mucha, G. Zwiehoff, “Built-in logic block observation techniques,”Proc. Int. Test Conf., pp. 37–41, 1979.
L. Wang, E. McCluskey, “Built-in self-test for sequential machines,Proc. Int. Test Conf., pp. 334–341, 1987.
B. Eschermann, H.-J. Wunderlich, “Optimized synthesis of self-testable finite state machines,”Dig. 20th Int. Symp. Fault-Tolerant Computing, pp. 390–397, 1990.
R.K. Brayton, G.D. Hachtel, C.T. McMullen, A.L. Sangiovanni-Vincentelli,Logic minimization algorithms for VLSI synthesis, Boston: Kluwer, 1984.
Octtools Distribution 4.0, Electronics Research Laboratory, University of California, Berkeley, 1990.
M.R. Garey, D. Johnson,Computers and Intractability, New York: Freeman, 1979.
H. Fujiwara, T. Shimono, “On the acceleration of test generation algorithms,”Dig. 13th Int. Symp. Fault-Tolerant Computing Syst., pp. 98–105, 1983.
M. Schulz, E. Auth, “Advanced automatic test pattern generation and redundancy identification techniques,”Dig. 18th Int. Symp. Fault-Tolerant Computing, pp. 30–35, 1988.
R.E. Bryant, “Graph-based algorithms for boolean function manipulation,”IEEE Trans. on Computers vol. C-35, pp. 677–691, 1986.
“Logic synthesis and optimization benchmarks, Version 2.0,” Microelectronics Center of North Carolina, 1988.
S.H. Robinson, J.P. Shen, “Direct methods for synthesis of self-monitoring state machines,”Proc. 22nd Int. Symp. on Fault-Tolerant Computing, pp. 306–315, 1992.
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Eschermann, B. Enhancing on-line testability during synthesis. J Electron Test 4, 105–116 (1993). https://doi.org/10.1007/BF00971943
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DOI: https://doi.org/10.1007/BF00971943