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On Test Generation for Microprocessors for Extended Class of Functional Faults

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VLSI-SoC: New Technology Enabler (VLSI-SoC 2019)

Part of the book series: IFIP Advances in Information and Communication Technology ((IFIPAICT,volume 586))

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Abstract

We propose a novel strategy of formalized synthesis of Software Based Self-Test (SBST) for testing microprocessors with RISC architecture to cover a large class of high-level functional faults. This is comparable to that used in memory testing which also covers a large class of structural faults such as stuck-at-faults (SAF), conditional SAF, multiple SAF and bridging faults. The approach is fully high-level, the model of the microprocessor is derived from the instruction set and architecture description, and no knowledge about gate-level implementation is needed. To keep the approach scalable, the microprocessor is partitioned into modules under test (MUT), and each MUT is in turn partitioned into data and control parts. For the data parts, pseudo-exhaustive tests are applied, while for the control parts, a novel generic functional control fault model was developed. A novel method for measuring high-level fault coverage for the control parts of MUTs is proposed. The measure can be interpreted as the quality of covering the high-level functional faults, which are difficult to enumerate. We apply High-Level Decision Diagrams for formalization and optimization of high-level test generation for control parts of modules and for trading off different test characteristics, such as test length, test generation time and fault coverage. The test is well-structured and can be easily unrolled online during test execution. Experimental results demonstrate high SAF coverage, achieved for a part of a RISC processor with known implementation, whereas the test was generated without knowledge of implementation details.

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Acknowledgments

The work was supported by EU H2020 project RESCUE, Estonian grant IUT 19-1, and Research Center EXCITE.

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Authors and Affiliations

  1. Centre for Dependable Computing Systems, Department of Computer Systems, Tallinn University of Technology, Akadeemia 15a, 12618, Tallinn, Estonia

    Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin & Jaan Raik

Authors
  1. Adeboye Stephen Oyeniran
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  2. Raimund Ubar
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  3. Maksim Jenihhin
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  4. Jaan Raik
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Corresponding author

Correspondence to Adeboye Stephen Oyeniran .

Editor information

Editors and Affiliations

  1. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil

    Carolina Metzler

  2. University of Utah, Salt Lake City, UT, USA

    Pierre-Emmanuel Gaillardon

  3. EPFL, Lausanne, Switzerland

    Giovanni De Micheli

  4. Pontificia Universidad Católica del Perú, Lima, Peru

    Carlos Silva-Cardenas

  5. Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil

    Ricardo Reis

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Oyeniran, A.S., Ubar, R., Jenihhin, M., Raik, J. (2020). On Test Generation for Microprocessors for Extended Class of Functional Faults. In: Metzler, C., Gaillardon, PE., De Micheli, G., Silva-Cardenas, C., Reis, R. (eds) VLSI-SoC: New Technology Enabler. VLSI-SoC 2019. IFIP Advances in Information and Communication Technology, vol 586. Springer, Cham. https://doi.org/10.1007/978-3-030-53273-4_2

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  • DOI: https://doi.org/10.1007/978-3-030-53273-4_2

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-53272-7

  • Online ISBN: 978-3-030-53273-4

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