Abstract
Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits. PLAs are often not suitable for random pattern testing due to high fao-in of gates. In order to reduce the effective fan-in of gates, previous random pattern testable (RPT) PLA designs focused on partitioning inputs and product lines. In this paper we propose a new random pattern testable design of PLAs which is suitable for built-in selftest. The key idea of the proposed design is to apply weighted random patterns to the PLA under test. The proposed design method was applied to 30 example PLAs. The performance of the RPT PLAs was measured in the size of test set, area overhead, and time overhead, and compared with two other designs in test length and fault coverage. The experimental results show that the proposed design achieve short test length and high fault coverage.
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References
V.K. Agarwal, “Multiple fault detection in programmable logic arrays,” IEEE Transactions Computers, vol. C-30, pp. 518–522, June 1980.
C.W. Cha, “A test strategy for PLAs,” Proc. 15th Design Auto. Conference, pp. 326–334, June 1978.
E.B. Eichelberger and E. Lindbloom, “A heuristic test pattern generation for programmable logic arrays,” IBM J. Res. Develop., vol. 24, pp. 15–22, Jan. 1980.
D.L. Ostapko and S.J. Hong, “Fault analysis and test generation for programmable logic arrays (PLA's),” IEEE Transactions Computers, vol. C-28, pp. 617–626, Sept. 1979.
J.E. Smith, “Detection of faults in programmable logic arrays,” IEEE Transactions Computers, vol. C-28, pp. 845–853, November 1979.
R.S. Wei and A. Sangiovanni-Vincentelli, “PLATYPUS: A PLA test pattern generation tool,” IEEE Transactions Computer-Aided Design, vol. CAD-5, pp. 633–644, October 1986.
S. Bozorgui-Nesbat and E.J. McCluskey, “Lower overhead design for testability of programmable logic arrays,” IEEE Transactions Computers, vol. C-35, pp. 379–383, April 1986.
H. Fujiwara, “A new PLA design for universal testability,” IEEE Transactions Computers, vol. C-33, pp. 745–750, August 1984.
D.S. Ha and S.M. Reddy, “On the design of testable domino PLAs,” Proc. Int. Test Conf., pp. 567–572, November 1985.
J. Khakbaz, “A testable PLA design with low overhead and high fault coverage,” IEEE Transactions Computers, vol. C-33, pp. 743–745, August 1984.
S.M. Reddy and D.S. Ha, “A new approach to the design of PLA's,” IEEE Transactions Computers., vol. C-36, pp. 201–211, February 1987.
D.S. Ha and S.M. Reddy, “On BIST PLAs,” Proc. Int. Test Conf., pp. 342–351, September 1987.
K.A. Hua, J.Y. Jou, and J.A. Abraham, “Built-in test for VLSI finite-state machines,” Proc. 14th Int. Symp. Fault-Tolerant Computing, pp. 302–307, June 1984.
D. Liu and E.J. McCluskey, “Design of large embedded CMOS PLAs for BIST,” IEEE Transactions Computer-Aided Design, vol. 7, pp. 50–59, January 1988.
J. Salick, M.R. Mercer and B. Underwood, “Built-in self-test input generator for programmable logic arrays,” Proc. Int. Test Conf., pp. 115–125, November 1985.
S.J. Upadhyaya and K.K. Saluja, “A new approach to design for BIST PLAs for high fault coverage,” IEEE Transactions Computer-Aided Design, vol. 7, pp. 60–67, January 1988.
R. Treuer, H. Fujiwara, and V. K. Agarwal, “Implementing a built-in self-test PLA design,” IEEE Design and Test of Computers, vol. 2, pp. 37–48, April 1985.
D.S. Ha and S.M. Reddy, “On the design of pseudo-exhaustive testable PLAs,” IEEE Transactions Computers, vol. C-37, pp. 468–472, April 1988.
E.B. Eichelberger and E. Lindbloom, “Random pattern coverage and diagnosis for LSSD logic self-test,” IBM J. Res. Develop., vol. 27, pp. 265–272, May 1983.
H. Fujiwara, “Design of PLA's with random pattern testability,” IEEE Transactions Computer-Aided Design, vol. 7, pp. 5–10, January 1988.
H. Fujiwara, “Enhancing random pattern coverage of programmable logic arrays via masking technique,” IEEE Transactions Computer-Aided Design, vol. 8, pp. 1022–1025, September 1989.
D.S. Ha and S.M. Reddy, “On the design of random pattern testable PLAs,” Proc. Int. Test Conf., pp. 688–695, September 1986.
H.D. Schnurmann, E. Lindbloom and R.G. Carpenter, “The weighted random test-pattern generator,” IEEE Transactions Computers, vol. C-24, pp. 695–700, July 1975.
P. Agrawal and V.D. Agrawal, “On improving the efficiency of Monte Carlo test generation,” Proc. Int. Symp. Fault-Tolerant Computing, pp. 392–398, 1975.
H.J. Wunderlich, “The random pattern testability of programmable logic arrays,” Proc. Int. Conf. on Comp. Design, pp. 682–685, 1987.
J.A. Waicukauski and E. Lindbloom, “Fault detection effectiveness of weighted random patterns,” Proc. Int. Test Conf., pp. 245–255, 1988.
R.K. Brayton, G.D. Hatchel, C.T. McMullen, and A. Sangiovanni-Vincentelli, Logic minimization algorithms for VLSI synthesis, Boston, MA: Kluwer Academic Publishers, 1984.
J.K. Ousterhout, G.T. Hanachi, R.N. Mayo, W.S. Scott and G.S. Taylor, “The magic VLSI layout system,” IEEE Design and Test of Computers, vol. 2, pp. 10–30, February 1985.
R.N. Mayo, “Unix programmer's manual—MPLA,” Document 9-F, Elec. Eng. Comput. Sci., Univ. of California, Berkeley, 1985.
C.A. Mead and L.A. Conway, “Introduction to VLSI systems,” Reading, MA: Addison-Wesley, 1980.
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Ha, D.S., Reddy, S.M. On the design of random pattern testable PLA based on weighted random pattern testing. J Electron Test 3, 149–157 (1992). https://doi.org/10.1007/BF00137252
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DOI: https://doi.org/10.1007/BF00137252