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Design Considerations and Optimization of Electrostatic Doped Ferroelectric Nanotube Tunnel FET: Analog and Noise Analysis

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Abstract

This paper proposed the electrostatically doped Ferroelectric Nanotube Tunnel FET (FE-NT-TFET). The proposed device is electrostatically doped, so the applied source voltage is -1.2 V (VS = -1.2 V). Device variables like potential variation, electric-field energy, non-local band to band electron tunnel (BTBT) rates, electron carrier concentration, and hole carrier concentration have been investigating. Analog variables like drain current (IDS), ION/IOFF current ratio, ON current (ION), sub-threshold slope (SS), OFF current (IOFF), a threshold voltage (VTH), and average sub-threshold slope (AVSS) have been discussed. The noise parameter such as real impedance (Z0), minimum noise figure (NF), auto/cross-correlation function (ACF & CCF) has been discussed. To obtain the steep sub-threshold slope (SS) and higher drain current (IDS) ferroelectric material is used in the place of the gate oxide. Ferroelectric material HfO2 is used in the proposed FE-NT-TFET device. HfO2 is used because of compatibility with the CMOS flow. The proposed FE-NT-TFET device shows the higher current 62.4uA/um for VDS = 1.2 V and steep sub-threshold slope (SS) 7 mV/decade. The proposed device shows the average sub-threshold slope (AVSS) 22.9 mV/decade. The proposed FE-NT-TFET device shows the lower OFF current (IOFF) order of 10−19A/um and higher ION/IOFF current order of 1013.

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Acknowledgements

The Author wish to thanks Dr Ashish Raman and Dr Naveen Kumar for his work in the field of semiconductor devices. We also thanks to the VLSI design Lab., Department of Electronics and communications, Dr B. R. Ambedkar National Institute of Technology, Jalandhar, 144011, India.

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  1. Department of Electronics and Communications, Dr. B. R. Ambedkar, National Institute of Technology, Jalandhar, 144011, India

    Ashok Kumar Gupta, Ashish Raman & Naveen Kumar

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  1. Ashok Kumar Gupta
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  2. Ashish Raman
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  3. Naveen Kumar
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Contributions

All the authors contributed to the study conception and design, literature review, material preparation, simulation, and analysis were performed by [Ashok Kumar Gupta], [Dr. Ashish Raman] and [Dr. Naveen Kumar]. The final draft of the manuscript was written by [Ashok Kumar Gupta] and all authors commented on the previous version of the manuscripts. All authors read and approved the final manuscript.

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Correspondence to Ashok Kumar Gupta.

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Highlights

• Design, Investigation and Optimization of Ferroelectric gate oxide based Electrostatic Doped Nanotube Tunnel TFET.

• For investigation and optimization purpose various parameters are varies like Work-function, Source Voltage, Channel length, and Ferro-dielectric width.

• The proposed device shows the better results as compare to the SiO2 based gate oxide.

• This work examines the maximum Noise-Figure (NFmax.), Auto-correlation factor, cross-correlation factor, and output impedance (real Z0).

• The proposed device shows the better noise reduction for ultra-high frequency applications

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Gupta, A.K., Raman, A. & Kumar, N. Design Considerations and Optimization of Electrostatic Doped Ferroelectric Nanotube Tunnel FET: Analog and Noise Analysis. Silicon 14, 10357–10373 (2022). https://doi.org/10.1007/s12633-022-01720-9

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