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Design and Self-Consistent Schrodinger-Poisson Model Simulation of Ultra-Thin Si-Channel Nanowire FET

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Abstract

Since at the regime of nanometer, the quantum confinement effects are observed and the wave nature of electrons is more dominant. Therefore, the classical approach of current formulation in mesoelectonics and nanoelectronics results in inaccuracy as it does not consider the quantum effect, which is only applicable for the bulk electronic device. For accurate modeling and simulation of nanoelectronics, device atomic-level quantum mechanical models are required. In this work, an ultra-thin (2 nm diameter) Silicon- channel Cylindrical Nanowire FET (CNWFET) is designed and simulated by invoking non-equilibrium green function (NEGF) formalism and self-consistent Schrodinger-Poisson’s equation model. Then impact variation of temperature, oxide thickness, and metal work function variation in the NWFET is investigated to analyze the distinct performance parameters of the device e.g. threshold voltage (Vth) drain induced barrier lowering (DIBL), sub-threshold swing (SS), and ION/IOFF ratio. The designed device exhibits reliable results and shows a SS of 57.8 mV/decade and ION to IOFF ratio of order 109 at room temperature.

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Current submission does not contain the pool data of the manuscript but the data used in the manuscript will be provided on request.

References

  1. Hoefflinger B (ed.) (2012) Chips 2020: a guide to the future of nanoelectronics. Springer Science & Business Media

  2. Cheung KP (2010, April) On the 60 mV/dec@ 300 K limit for MOSFET subthreshold swing. In: Proceedings of 2010 international symposium on VLSI technology, system and application (pp. 72-73). IEEE

  3. Singh J, Verma C (2021) Modeling methods for nanoscale semiconductor devices. Silicon, pp.1–8

  4. Sahay S, Kumar MJ (2017) Diameter dependence of leakage current in nanowire junctionless field effect transistors. IEEE Trans Electron Devices 64(3):1330–1335

    Article  Google Scholar 

  5. Tamersit K (2020) Improved performance of nanoscale junctionless carbon nanotube tunneling FETs using dual-material source gate design: a quantum simulation study. AEU-Int J Electron Commun 127:153491

    Article  Google Scholar 

  6. Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong HSP (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proc IEEE 89(3):259–288

    Article  CAS  Google Scholar 

  7. Wadhwa G, Singh J (2020) Implementation of linearly modulated work function a σ B 1− σ gate electrode and Si 0.55 Ge 0.45 N+ pocket doping for performance improvement in gate stack vertical-TFET. Appl Phys A Mater Sci Process 126(11):1–11

    Article  Google Scholar 

  8. Moore GE (1965) Cramming more components onto integrated circuits. Electronics 38(8):114

    Google Scholar 

  9. Bayani AH, Voves J, Dideban D (2018) Effective mass approximation versus full atomistic model to calculate the output characteristics of a gate-all-around germanium nanowire field effect transistor (GAA-GeNW-FET). Superlattice Microst 113:769–776

    Article  CAS  Google Scholar 

  10. Kumar S, Raj B (2015) Compact channel potential analytical modeling of DG-TFET based on evanescent-mode approach. J Comput Electron 14(3):820–827

    Article  CAS  Google Scholar 

  11. Verma C, Singh J, Wadhwa G (2020, July) Design and performance analysis of FD silicon on insulator MOSFET. In: 2020 IEEE students conference on Engineering & Systems (SCES) (pp. 1-6). IEEE

  12. Singh J, Chakraborty D, Kumar N (2021) Design and parametric variation assessment of Dopingless nanotube field-effect transistor (DL-NT-FET) for high performance. Silicon, pp1–9

  13. Kumar N, Raman A (2019) Design and investigation of charge-plasma-based work function engineered dual-metal-heterogeneous gate Si-Si 0.55 Ge 0.45 GAA-cylindrical NWTFET for ambipolar analysis. IEEE Trans Electron Devices 66(3):1468–1474

    Article  CAS  Google Scholar 

  14. Singh A, Khosla M, Raj B (2017) Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM. AEU-Int J Electron Commun 80:67–72

    Article  Google Scholar 

  15. Appenzeller J, Lin YM, Knoch J, Avouris P (2004) Band-to-band tunneling in carbon nanotube field-effect transistors. Phys Rev Lett 93(19):196805

    Article  CAS  Google Scholar 

  16. Lundstrom M, Ren Z (2002) Essential physics of carrier transport in nanoscale MOSFETs. IEEE Trans Electron Devices 49(1):133–141

    Article  Google Scholar 

  17. Dash TP, Dey S, Das S, Mohapatra E, Jena J, Maiti CK (2020) Strain-engineering in nanowire field-effect transistors at 3 nm technology node. Phys E: Low-Dimensional Syst Nanostruct 118:113964

    Article  CAS  Google Scholar 

  18. Bangsaruntip S, Majumdar A, Cohen GM, Engelmann SU, Zhang Y, Guillorn M, Gignac LM, Mittal S, Graham WS, Joseph EA, Klaus DP (2010, June) Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm. In: 2010 symposium on VLSI technology (pp. 21-22). IEEE

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All authors have equally participated in the prep aring of the manuscript during implementation of ideas, findings result, and writing of the manuscript.

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Correspondence to Jeetendra Singh.

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Verma, C., Singh, J. Design and Self-Consistent Schrodinger-Poisson Model Simulation of Ultra-Thin Si-Channel Nanowire FET. Silicon 14, 6185–6191 (2022). https://doi.org/10.1007/s12633-021-01388-7

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  • DOI: https://doi.org/10.1007/s12633-021-01388-7

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