Abstract
In this work, the characteristics of linearly graded work function (LGW) by utilizing the composition of binary metal alloy AσB1−σ gate electrode and the characteristics of Si-Si0.55Ge0.45 middle N+ pocket heterojunction at the interface of source and channel is explored in the high-k gate stack vertical-TFET (GS-VTFET). The proposed novel structure of VTFET is gradually developed from the single metal gate work function to linearly graded work function of binary metal alloy gate with and without incorporating the Si0.55Ge0.45 N+ pocket and then their various performance parameters of the design are compared. The combined effects of LGW and Si0.55Ge0.45 N+ pocket in GS-VTFET (GS-LGWN-VTFET) show high-performance improvement in subthreshold slope (SS), ON-current (ION), and transconductance generation efficiency (TGE) without affecting the OFF-current (IOFF). GS-LGWN-VTFET renders 5 mV/dec SS, which is 85% lower than the SS of gate stack-single metal work function (GS-SGW-VTFET), and also it exhibits 1 order higher ION keeping the ION/IOFF ratio 1012. Low bandgap Si–Si0.55Ge0.45 N+ causes narrow band-bending and thus results in high tunneling and steeper SS whereas further scaling in SS is possible due to the inclusion of the LGW, which sharps the electrons tunneling rate.
Similar content being viewed by others
References
U.E. Avci, D.H. Morris, I.A. Young, Tunnel field-effect transistors: Prospects and challenges. IEEE J. Electron Devices Soc. 3(3), 88–95 (2015)
N. Bagga, S. Dasgupta, Surface potential and drain current analytical model of gate all around triple metal TFET. IEEE Trans. Electron Devices 64(2), 606–613 (2017)
X. Duan, J. Zhang, S. Wang, Y. Li, S. Xu, Y. Hao, A high-performance gate engineered InGaN dopingless tunnel FET. IEEE Trans. Electron Devices 65(3), 1223–1229 (2018)
S.K. Gupta, S. Kumar, Analytical modeling of a triple material double gate TFET with hetero-dielectric gate stack. Silicon 11(3), 1355–1369 (2019)
V. Dharshan, N.B. Balamurugan, T.S. Samuel, An analytical modeling and simulation of surrounding gate TFET with an impact of dual material gate and stacked oxide for low power applications. J. Nano Res. 57, 68–76 (2019)
F. Settino, M. Lanuzza, S. Strangio, F. Crupi, P. Palestri, D. Esseni, L. Selmi, Understanding the potential and limitations of tunnel FETs for low-voltage analog/mixed-signal circuits. IEEE Trans. Electron Devices 64(6), 2736–2743 (2017)
A. Villalon, G. Le Carval, S. Martinie, C. Le Royer, M.A. Jaud, S. Cristoloveanu, Further insights in TFET operation. IEEE Trans. Electron Devices 61(8), 2893–2898 (2014)
E. Ko, H. Lee, J.D. Park, C. Shin, Vertical tunnel FET: design optimization with triple metal-gate layers. IEEE Trans. Electron Devices 63(12), 5030–5035 (2016)
S.S. Chauhan, A new design approach to improve DC, analog/RF and linearity metrics of vertical TFET for RFIC design. Superlattices Microstruct. 122, 286–295 (2018)
Zhang, J.H., STMicroelectronics lnc, 2017. Vertical gate-all-around TFET. U.S. Patent 9,653,585.
T.J.K. Liu, S.H. Kim, Tunnel FET promise and challenges. In: Extended abstract of international conference on solid-state devices and materials, pp. C-3–1, Tokyo, Japan (2010)
R. Pandey, S. Mookerjea, S. Datta, Opportunities and challenges of tunnel FETs. IEEE Trans. Circuits Syst. I Regul. Pap. 63(12), 2128–2138 (2016)
R. Li, Y. Lu, S.D. Chae, G. Zhou, Q. Liu, C. Chen, M. Shahriar Rahman, T. Vasen, Q. Zhang, P. Fay, T. Kosel, InAs/AlGaSb heterojunction tunnel field-effect transistor with tunnelling in-line with the gate field. Phys. Status Solidi C 9(2), 389–392 (2012)
B.R. Raad, K. Nigam, D. Sharma, P.N. Kondekar, Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement. Superlattices Microstruct. 94, 138–146 (2016)
A.M. Walke, A. Vandooren, R. Rooyackers, D. Leonelli, A. Hikavyy, R. Loo, A.S. Verhulst, K.H. Kao, C. Huyghebaert, G. Groeseneken, V.R. Rao, Fabrication and analysis of a Si/Si0.55 Ge0.45 heterojunction line tunnel FET. IEEE Trans. Electron Devices 61(3), 707–715 (2014)
S.H. Kim, S. Agarwal, Z.A. Jacobson, P. Matheu, C. Hu, T.J.K. Liu, Tunnel field effect transistor with raised germanium source. IEEE Electron Device Lett. 31(10), 1107–1109 (2010)
G.B. Beneventi, E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani, Dual-metal-gate InAs tunnel FET with enhanced turn-on steepness and high on-current. IEEE Trans. Electron Devices 61(3), 776–784 (2014)
S. Safa, S.L. Noor, Z.R. Khan, Physics-based generalized threshold voltage model of multiple material gate tunneling FET structure. IEEE Trans. Electron Devices 64(4), 1449–1454 (2017)
P. Vimala, T.A. Samuel, D. Nirmal, A.K. Panda, Performance enhancement of triple material double gate TFET with heterojunction and heterodielectric. Solid State Electron. Lett. 1(2), 64–72 (2019)
S. Deb, N.B. Singh, N. Islam, S.K. Sarkar, Work function engineering with linearly graded binary metal alloy gate electrode for short-channel SOI MOSFET. IEEE Trans. Nanotechnol. 11(3), 472–478 (2011)
B.Y. Tsui, C.F. Huang, Wide range work function modulation of binary alloys for MOSFET application. IEEE Electron Device Lett. 24(3), 153–155 (2003)
K. Boucart, A.M. Ionescu, Double-gate tunnel FET with high gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007). https://doi.org/10.1109/.TED.2007.899389
R. Vaddi, R.P. Agarwal, S. Dasgupta, Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied–independent gate and symmetric–asymmetric options. Microelectron. J. 42(5), 798–807 (2011). https://doi.org/10.1016/j.mejo.2011.01.004
Y. Taur, D. Buchanan, W. Chen, D.J. Frank, K.I. Ismail, S.-H. Lo, G.A. Sai-Halasz, R.G. Viswanathan, H.-J.C. Wann, S.J. Wind, H.-S. Wong, CMOS scaling into the nanometer regime. Proc. IEEE 85, 486–504 (1997)
B. Manna, S. Sarkhel, N. Islam, S. Sarkar, S.K. Sarkar, Spatial composition grading of binary metal alloy gate electrode for short-channel SOI/SON MOSFET application. IEEE Trans. Electron Devices 59(12), 3280–3287 (2012)
N. Bagga, S. Sarkhel, S.K. Sarkar, Exploring the asymmetric characteristics of a double gate MOSFET with linearly graded binary metal alloy gate electrode for enhanced performance. IETE J. Res. 62(6), 786–794 (2016)
H.M. Christen, S.D. Silliman, K.S. Harshavardhan, Continuous compositional-spread technique based on pulsed-laser deposition and applied to the growth of epitaxial films. Rev. Sci. Instrum. 72(6), 2673–2678 (2001)
I. Ohkubo, H.M. Christen, P. Khalifah, S. Sathyamurthy, H.Y. Zhai, C.M. Rouleau, D.G. Mandrus, D.H. Lowndes, Continuous composition-spread thin films of transition metal oxides by pulsed-laser deposition. Appl. Surf. Sci. 223(1–3), 35–38 (2004)
A. Pan, R. Liu, M. Sun, C.Z. Ning, Spatial composition grading of quaternary ZnCdSSe alloy nanowires with tunable light emission between 350 and 710 nm on a single substrate. ACS Nano 4(2), 671–680 (2010)
A. Sadek, K. Ismail, M.A. Armstrong, D.A. Antoniadis, F. Stern, Design of Si/SiGe heterojunction complementary metal-oxide-semiconductor transistors. IEEE Trans. Electron Devices 43(8), 1224–1232 (1996)
K.K. Young, Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans. Electron Devices 36(2), 399–402 (1989)
R. Ishii, K. Matsumura, A. Sakai, T. Sakata, Work function of binary alloys. Appl. Surf. Sci. 169, 658–661 (2001)
TCAD Silvaco, atlas, Version 5.15.32.R. (2009) [Online]. Available: https://www.silvaco.com.
M.J. Chen, W.H. Lee, Y.H. Huang, Error-free Matthiessen’s rule in the MOSFET universal mobility region. IEEE Trans. Electron Devices 60(2), 753–758 (2013)
E.O. Kane, Theory of tunneling. J. Appl. Phys. 32(1), 83–91 (1961)
K.H. Kao, A.S. Verhulst, R. Rooyackers, B. Douhard, J. Delmotte, H. Bender, O. Richard, W. Vandervorst, E. Simoen, A. Hikavyy, R. Loo, Compressively strained SiGe band-to-band tunneling model calibration based on pin diodes and prospect of strained SiGe tunneling field-effect transistors. J. Appl. Phys. 116(21), 214506 (2014)
A. Schenk, A model for the field and temperature dependence of Shockley-Read-Hall lifetimes in silicon. Solid-State Electronics 35(11), 1585–1596 (1992)
M.E. Levinshtein, S.L. Rumyantsev, M.S. Shur, Properties of Advanced Semiconductor Materials: GaN, AIN, InN, BN, SiC, SiGe (Wiley, New York, 2001)
C.G. Van de Walle, R.M. Martin, Theoretical calculations of heterojunction discontinuities in the Si/Ge system. Phys. Rev. B 34(8), 5621 (1986)
R.A. Logan, J.M. Rowell, F.A. Trumbore, Phonon spectra of Ge–Si alloys. Phys. Rev. 136(6A), A1751 (1964)
R. Braunstein, A.R. Moore, F. Herman, Intrinsic optical absorption in germanium–silicon alloys. Phys. Rev. 109(3), 695 (1958)
People, R, Physics and applications of Gex Si1–x/Si strained-layer heterostructures. IEEE J. Quantum Electron. 22(9), 1696–1710 (1986)
M.V. Fischetti, S.E. Laux, Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys. J. Appl. Phys. 80(4), 2234–2252 (1996)
K. Boucart, A.M. Ionescu, Threshold voltage in tunnel FETs: physical definition, extraction, scaling and impact on IC design. In: ESSDERC 2007–37th European solid state device research conference (pp. 299–302). IEEE (2007)
P. Kumar, B. Bhowmick, Comparative analysis of hetero gate dielectric hetero structure tunnel FET and Schottky Barrier FET with n+ pocket doping for suppression of ambipolar conduction and improved RF/linearity. J. Nanoelectron. Optoelectron. 14(2), 261–271 (2019)
S. Dash, G.S. Sahoo, G.P. Mishra, Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate. Superlattices Microstruct. 91, 105–111 (2016)
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Wadhwa, G., Singh, J. Implementation of linearly modulated work function AσB1−σ gate electrode and Si0.55Ge0.45 N+ pocket doping for performance improvement in gate stack vertical-TFET. Appl. Phys. A 126, 877 (2020). https://doi.org/10.1007/s00339-020-04065-5
Received:
Accepted:
Published:
DOI: https://doi.org/10.1007/s00339-020-04065-5