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Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap

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Abstract

In this work, a novel structure of Gate-all-Around Si-Nanotube Tunnel FET (GAA Si-NTTFET) has been proposed to improve its electrical characteristics by overlapping a portion of source with its gate terminal. Using 3-D TCAD simulation, it has been found that the on-state current and subthreshold swing of GAA Si-NTTFET can be significantly improved with an optimum length of gate-source overlapping (GSO) i.e. 27-nm only, thus not limiting the scalability of source region. Furthermore, GSO has also caused a reduction in the turn-on voltage of GAA Si-NTTFET which may help to scaling the supply voltages. Moreover, due to reduction in the lateral electric field at source-channel interface caused by GSO, the off-state current has been observed to be smaller as compared to the conventional GAA Si-NTTFET which eventually reduces the stand-by power dissipation. Additionally, the ambipolar current has also been found to be reduced in the proposed structure which makes it more suitable for its application in the digital circuits.

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Data Availability

This is the simulated work and the old papers on the same topic is only the required materials and the simulation performed on the TAD tool.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Adama Science and Technology University, Adama, Ethiopia

    Avtar Singh

  2. School of Electronics Engineering, VIT-AP University, Amravati, Andhra Pradesh, India

    Chandan Kumar Pandey

Authors
  1. Avtar Singh
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  2. Chandan Kumar Pandey
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Both the authors equally contributed for the preparation of the manuscript

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Correspondence to Avtar Singh.

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This is the new work and submitted to any journal first time. The manuscript is prapred as the ethical standard.

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Singh, A., Pandey, C.K. Improved DC Performances of Gate-all-around Si-Nanotube Tunnel FETs Using Gate-Source Overlap. Silicon 14, 1463–1470 (2022). https://doi.org/10.1007/s12633-021-00957-0

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