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Effect of Temperature on Reliability Issues of Ferroelectric Dopant Segregated Schottky Barrier Tunnel Field Effect Transistor (Fe DS-SBTFET)

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Abstract

This paper addresses reliability issues associated with temperature of Ferroelectric Dopant Segregated Schottky Barrier Tunnel Field Effect Transistor (Fe DS-SBTFET). The simulated results are compared with Dopant Segregated Schottky Barrier TFET (DS-SBTFET). This is achieved by varying the operating temperature from 300 to 500 K. DC parameters such as ION/IOFF ratio, drain current characteristics and subthreshold swing (SS) for a range of temperature have been highlighted. Moreover, the influence of temperature on various RF figure of merits such as gate capacitance (CGG), intrinsic delay, cutoff frequency (fT) etc. have been investigated. The device linearity has been analyzed by considering the effect of temperature variation on linearity parameters like gm2, gm3, 1-dB compression point, VIP2, VIP3 and IIP3. The device characteristics get upgraded by the increase in cut-off frequency and reduction in intrinsic delay at elevated temperature.

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References

  1. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy efficient electronic switches. Nature 479:329–337

    Article  CAS  Google Scholar 

  2. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-K gate dielectric. IEEE Trans Electron Devices 54:1725–1733

    Article  CAS  Google Scholar 

  3. Khatami Y, Banerjee K (2009) Steep subthreshold slope n- and p-type tunnel-FET devices for low-power and energy-efficient digital circuits. IEEE Trans Electron Devices 56:2752–2761

    Article  CAS  Google Scholar 

  4. Jhaveri R, Woo J (2006) Schottky tunneling source MOSFET design for mixed mode and analog applications. 2006 European solid-state device research conference, Montreux, 295–298

  5. Kim J, Jhaveri R, Woo JCS, Yang CK (2011) Circuit-level performance evaluation of schottky tunneling transistor in mixed signal applications. IEEE Trans Nanotech 10:291–299

    Article  Google Scholar 

  6. Singh S, Kondekar PN (2017) A novel electrostatically doped ferroelectric Schottky barrier tunnel FET: process resilient design. J Comput Electron 16:685–695

    Article  CAS  Google Scholar 

  7. Larson JM, Snyder JP (2006) Overview and status of metal S/D Schottky-barrier MOSFET technology. IEEE Trans Electron Devices 53:1048–1058

    Article  CAS  Google Scholar 

  8. Östling M, Luo J, Gudmundsson V, Hellström P, Malm B G (2010) Nanoscaling of MOSFETs and the implementation of Schottky barrier S/D contacts. 2010 27th international conference on microelectronics proceedings, Nis, 9–13

  9. Kinoshita A, Tsuchiya Y, Yagishita A, Uchida K, Koga J (2004) Solution for high-performance Schottky source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique. VLSI Symposium Technology Digest 168–169

  10. Knoch J, Zhang M, Zhao T, Lenk SS (2005) Effective Schottky barrier lowering in silicon-on-insulator Schottky barrier metal-oxide semiconductor field-effect transistor using dopant segregation. Appl Phys Lett 87:263505–263507

    Article  Google Scholar 

  11. Salahuddin S, Datta S (2008) Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett 8:405–410

    Article  CAS  Google Scholar 

  12. Khan AI, Chatterjee K, Wang B, Drapcho S, You L, Serrao C, Salahuddin S (2015) Negative capacitance in a ferroelectric capacitor. Nat Mater 14:182–186

    Article  CAS  Google Scholar 

  13. Jimenez D, Miranda E, Godoy A (2010) Analytic model for the surface potential and drain current in negative capacitance field-effect transistors. IEEE Trans Electron Devices 57:2405–2409. https://doi.org/10.1109/TED.2010.2062188

    Article  Google Scholar 

  14. Khan AI, Yeung CW, C Hu, Salahuddin S (2011) Ferroelectric negative capacitance MOSFET: capacitance tuning and antiferroelectric operation. Electron Devices Meeting (IEDM), IEEE Int. 11.3.1–11.3.4. https://doi.org/10.1109/IEDM.2011.6131532

  15. Ghosh P, Bhowmick B (2019) Optimisation of electrical parameters in Fe DSSBTFET and its application as a digital inverter. Int J Electron:1–15. https://doi.org/10.1080/00207217.2019.1600744

  16. Kobayashi M, Jang K, Ueyama N, Hiramoto T (2017) Negative capacitance for boosting tunnel FET performance. IEEE Trans Nanotechnol 16:253–258

    Article  CAS  Google Scholar 

  17. Schlom D, Chen L-Q, Pan X, Schmehl A, Zurbuchen MA (2008) A thin film approach to engineering functionality into oxides. J Am Ceram Soc 91:2429–2454

    Article  CAS  Google Scholar 

  18. T.C.A.D. Synopsys, Manual, ver E2010.12

  19. Jhaveri R, Nagavarapu V, Woo J (2009) Asymmetric Schottky tunneling source SOI MOSFET design for mixed mode applications. IEEE Trans Electron Devices 56:93–99

    Article  CAS  Google Scholar 

  20. Madan J, Chaujar R (2016) Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET. 2016 IEEE International Nanoelectronics Conference (INEC), Chengdu, 1–2. https://doi.org/10.1109/INEC.2016.7589278

  21. Narang R, Saxena M, Gupta RS, Gupta M (2013) Impact of temperature variations on the device and circuit performance of tunnel FET: a simulation study. IEEE Trans Nanotechnol 12:951–957

    Article  CAS  Google Scholar 

  22. Saha R, Bhowmick B, Baishya S (2018) Temperature effect on RF/analog and linearity parameters in DMG FinFET. Appl Phys A Mater Sci Process 124(642). https://doi.org/10.1007/s00339-018-2068-5

  23. Ma T, Han J-P (2002) Why is nonvolatile ferroelectric memory field-effect transistor still elusive? IEEE Electron Device Lett 23:386–388

    Article  CAS  Google Scholar 

  24. Mohapatra S, Pradhan K, Sahu P (2015) Temperature dependence inflection point in ultra-thin Si directly on insulator (SDOI) MOSFETs: an influence to key performance metrics. Superlattice Microst 78:134–143

    Article  CAS  Google Scholar 

  25. Kranti A, Armstrong GA (2010) Nonclassical Channel design in MOSFETs for improving OTA gain-bandwidth trade-off. IEEE Trans Circuits Syst Regul Pap 57:3048–3054

    Article  Google Scholar 

  26. Gautam R, Saxena M, Gupta RS, Gupta M (2012) Effect of localised charges on nanoscale cylindrical surrounding gate MOSFET: analog performance and linearity analysis. Microelectron Reliab 52:989–994

    Article  CAS  Google Scholar 

  27. Rawat AS, Gupta SK (2017) Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications. Microelectron J 66:89–102

    Article  CAS  Google Scholar 

  28. Kumar SP, Agrawal A, Chaujar R, Gupta RS, Gupta M (2011) Device linearity and intermodulation distortion comparison of dual material gate and conventional AlGaN/GaN high electron mobility transistor. Microelectron Reliab 51:587–596

    Article  CAS  Google Scholar 

  29. Ghosh P, Haldar S, Gupta RS, Gupta M (2012) An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design. IEEE Trans Electron Devices 59:3263–3268

    Article  Google Scholar 

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Correspondence to Puja Ghosh.

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Ghosh, P., Bhowmick, B. Effect of Temperature on Reliability Issues of Ferroelectric Dopant Segregated Schottky Barrier Tunnel Field Effect Transistor (Fe DS-SBTFET). Silicon 12, 1137–1144 (2020). https://doi.org/10.1007/s12633-019-00206-5

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