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Impact of an Elevated Temperature Environment on Sn-Ag-Cu Interconnect Board Level High-G Mechanical Shock Performance

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Abstract

The mechanical stability of Sn-Ag-Cu interconnects with low and high silver content against mechanical shock at room and elevated temperatures was investigated. With a heating element-embedded printed circuit board design, a test temperature from room temperature to 80°C was established. High impact shock tests were applied to isothermally pre-conditioned ball-grid array interconnects. Under cyclic shock testing, degradation and improved shock performances were identified associated with test temperature variation and non-solder mask defined and solder-mask defined pad design configuration differences. Different crack propagation paths were observed, induced by the effect of the elevated temperature test conditions and isothermal aging pre-conditions.

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References

  1. T. Mattila, J. Hokka, and M. Paulasto-Krockel, J. Electron. Mater. 43, 4090 (2014).

    Article  Google Scholar 

  2. D.R. Frear and P.T. Vianco, Metall. Trans. A 25A, 1509 (1994).

    Article  Google Scholar 

  3. J. Glazer, Int. Mater. Rev. 40, 65 (1995).

    Article  Google Scholar 

  4. K. Yazzie, H. Fei, J. Williams, H. Jiang, and N. Chawla, J. Electron. Mater. 38, 2746 (2009).

    Article  Google Scholar 

  5. H.G. Song, J.W. Morris Jr., and F. Hua, JOM 56, 30 (2002).

    Article  Google Scholar 

  6. H.K. Kim and K.N. Tu, Phys. Rev. B 53, 16027 (1996).

    Article  Google Scholar 

  7. T.-K. Lee, C. Kim, and T. Bieler, J. Electron. Mater. 43, 69 (2014).

    Article  Google Scholar 

  8. T.-K. Lee, B. Zhou, T. Bieler, C. Tseng, and J. Duh, J. Electron. Mater. 42, 215 (2013).

    Article  Google Scholar 

  9. T.-K. Lee, W. Xie, and C. Guirguis, in Proceeding of IEEE 65th Electronic Components and Technology Conference (2015), pp. 1560–1565.

  10. V. Fiori, K. Ewuame, S. Lallois-Garreignot, H. Jaouen, and C. Tavernier, Microelectron. Reliab. 54, 764 (2014).

    Article  Google Scholar 

  11. J. Karppinen, T. Laurila, T. Mattila, and M. Paulasto-Krockel, J. Electron. Mater. 41, 3232 (2012).

    Article  Google Scholar 

  12. B. Noh, J. Yoon, S. Ha, and S. Jung, J. Electron. Mater. 40, 224 (2011).

    Article  Google Scholar 

  13. W. Peng and M.E. Marques, J. Electron. Mater. 36, 1679 (2007).

    Article  Google Scholar 

  14. JEDEC JC-14 Committee, Board Level Drop Test Method of Components for Handheld Electronic Products (JEDEC Standard JESD22-B111, 2003). www.jedec.org/standards- documents/docs/jesd-22-b111.

  15. J. Savic, M. Nagar, W. Xie, M. Ahmad, D. Senk, A. Bansal, N. Islam, P. Oh, R. Pendse, H. Choi, and S. Lee, in Proceeding of IEEE 62nd Electronic Components and Technology Conference (2012), pp. 450–456.

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Correspondence to Tae-Kyu Lee.

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Lee, TK., Chen, Z., Baty, G. et al. Impact of an Elevated Temperature Environment on Sn-Ag-Cu Interconnect Board Level High-G Mechanical Shock Performance. J. Electron. Mater. 45, 6177–6183 (2016). https://doi.org/10.1007/s11664-016-4902-x

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  • DOI: https://doi.org/10.1007/s11664-016-4902-x

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