Abstract
In concurrent online BIST, testing is conducted simultaneously during normal functional operation. A fault model enables a structural test to be undertaken for a long time while simultaneously identifying critical faults. As a result of continuous testing, intermittent and transient faults are more likely to be detected. The number of required cycles for completion of a concurrent test, known as concurrent test latency (CTL), is a critical parameter for a concurrent BIST design. Most of the existing methods have impractical CTL, while others suffer from a high hardware overhead or a presence of a substantial combinational circuit. These methods are also incompatible with situations where parameters need to be adjusted, like when the hardware is more critical than CTL and vice versa. This paper proposes an efficient concurrent BIST to overcome the mentioned challenges. The main components of the proposed design consist of LFSRs and a small decoding combinational module result in low hardware overhead. In addition, CTL and hardware overhead can be adjusted and tuned in an acceptable range using the proposed method. Compared to the most efficient method, the proposed method achieves a 10% reduction in hardware overhead for large-scale circuits by keeping the CTL minimum. The different experiments demonstrate the capability of tuning between CTL and hardware overhead for the proposed BIST design. In the case that CTL and hardware overhead are equally important, the proposed method significantly lowers CTL compared to previous methods, while hardware overhead is only about 4% higher than previous method for both large scale (LS) and very large scale (VLS) circuits.
Similar content being viewed by others
Data Availability
The datasets generated and/or analyzed during the present study are available from the corresponding author on reasonable request.
References
Abirami S, Paulin NS, S. Venkateshwaran SP (2015) A concurrent BIST architecture for online input vector monitoring. International Conference on Science, Technology and Management (ICSTM), New Delhi, India, pp 1411–1417
Abramovici M, Breuer M, Friedman A (1990) Digital Systems Testing and Testable Design. Computer Science Press
Askarzadeh M, Haghparast M, Jabbehdari S (2021) Power consumption reduction in built-in self-test circuits. J Ambient Intell Humaniz Comput 14:1109–1122
Biswas S, Das SR, Petriu EM (2006) Space compactor design in VLSI circuits based on graph theoretic concepts. IEEE Trans Instrum Meas 55(4):1106–1118
Divyapreethi B, Karthik T (2015) Input vector monitoring concurrent BIST architecture using modified SRAM cells. ARPN J Eng Appl Sci 10(9):4042–4046
Jurj SL, Rotar R, Opritoiu F, Vladutiu M (2020) Online Built-In Self-Test Architecture for Automated Testing of a Solar Tracking Equipment. In: Proc. IEEE International Conference on Environment and Electrical Engineering and IEEE Industrial and Commercial Power Systems Europe (EEEIC/I&CPS Europe), pp 1-7
Kochte MA, Zoellin CG, Wunderlich H-J (2010) Efficient concurrent self-test with partially specified patterns. J Electron Test 26(5):581–594
Menbari A, Jahanirad H (2020) A Concurrent BIST Architecture for Combinational Logic Circuits. In: Proc. 10th International Conference on Computer and Knowledge Engineering (ICCKE), pp 262–267
Menbari A, Jahanirad H (2022) A low-cost BIST design supporting offline and online tests. J Electron Test 38(1):107–123
Murugan SV, Sathiyabhama B (2021) Bit-swapping linear feedback shift register (LFSR) for power reduction using pre-charged XOR with multiplexer technique in built in self-test. J Ambient Intell Humaniz Comput 12(6):6367–6373
Pavlidis A, Louërat MM, Faehn E, Kumar A, Stratigopoulos H-G (2021) SymBIST: Symmetry-based analog and mixed-signal built-in self-test for functional safety. IEEE Transactions on Circuits and Systems I: Regular Papers 68(6):2580–2593
Saluja KK, Sharma R, Kime CR (1987) Concurrent comparative testing using BIST resources. In: Proc. International Conference on Computer Aided Design, pp 336–339
Saluja KK, Sharma R, Kime CR (1987) Concurrent comparative built-in testing of digital circuits. University of Wisconsin, Engineering Experiment Station, Madison, Wisconsin, USA
Saluja KK, Sharma R, Kime CR (1988) A concurrent testing technique for digital circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 7(12):1250–1260
Shivakumar V, Senthilpari C, Yusoff Z (2021) A low-power and area-efficient design of a weighted pseudorandom test-pattern generator for a test-per-scan built-in self-test architecture. IEEE Access 9:29366–29379
Voyiatzis I (2012) Input Vector Monitoring On line Concurrent BIST based on multilevel decoding logic. In: Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1251–1256
Voyiatzis I, Efstathiou C (2013) Input vector monitoring concurrent BIST architecture using SRAM cells. IEEE Trans Very Large-Scale Integr (VLSI) Syst 22(7):1625–1629
Voyiatzis I, Halatsis C (2005) A low-cost concurrent BIST scheme for increased dependability. IEEE Transactions on Dependable and Secure Computing 2(2):150–156
Voyiatzis I, Paschalis A, Gizopoulos D, Halatsis C, Makri FS, Hatzimihail M (2008) An input vector monitoring concurrent BIST architecture based on a precomputed test set. IEEE Transactions on Computers 57(8):1012–1022
Voyiatzis I, Paschalis A, Gizopoulos D, Kranitis N, Halatsis C (2005) A concurrent built-in self test architecture based on a self-testing RAM. IEEE Trans Reliab 54(1):69–78
Wu TB, Liu HZ, Liu PX, Guo DS, Sun HM (2013) A cost-efficient input vector monitoring concurrent online BIST scheme based on multi-level decoding logic. J Electron Test 29(4):585–600
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
Conflict of Interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Additional information
Responsible Editor: K. K. Saluja
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
About this article
Cite this article
Menbari, A., Jahanirad, H. A Tunable Concurrent BIST Design Based on Reconfigurable LFSR. J Electron Test 39, 245–262 (2023). https://doi.org/10.1007/s10836-023-06055-w
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-023-06055-w