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Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications

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Abstract

In this research paper, approximate multipliers are designed to reduce the computational time and power delay product. However, there is a high possibility to further optimize the area and power using the modified Wallace Tree Multiplier (MWTM). This research paper proposes, two modified approximate 4:2 compressors are used for partial product addition in multipliers. Using the proposed MWTM, it is observed that Normalized Error Distance (NMED), Mean Relative Error Distance (MRED) and Power Delay Product (PDP) are reduced. The proposed architectures are synthesized using 90-nm CMOS standard cells. Modified Wallace tree multipliers of various sizes (8, 16 and 32 bit) are designed and their performance is compared with the existing general multipliers. The synthesis results of 8-bit MWTM shows that on an average the delay and power are reduced in the range of 10%–55.37% and 13.03%–13.78% when compared to existing multipliers. Moreover, for 16-bit MWTM shows that on an average the delay and power are reduced in the range of 0.11%–3.12% and 0.28%–6.59%. And 32-bit MWTM shows that on an average the power is reduced in the range of about 8%–27.99%. The image processing operations image blending, image smoothening and edge detection are implemented using the proposed MWTM. The results proved the efficiency of the MWTM.

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Authors and Affiliations

  1. IT Application Developer, Legato Health Technologies, Bangalore, Karnataka, India

    Shravani Chandaka

  2. Department of Electronics and Communication Engineering, JNTUK, Kakinada, Andhra pradesh, India

    Balaji Narayanam

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  1. Shravani Chandaka
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Correspondence to Shravani Chandaka.

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Chandaka, S., Narayanam, B. Hardware Efficient Approximate Multiplier Architecture for Image Processing Applications. J Electron Test 38, 217–230 (2022). https://doi.org/10.1007/s10836-022-06000-3

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