Abstract
The synthesis of reversible circuits is a challenge on which many studies have been conducted. Different algorithms attempt to propose a more optimal implementation for each description of a reversible circuit, using reversible gates. In this paper, an algorithm is proposed which, by a heuristic method using a Simulated Annealing algorithm, tries to find a near-optimal circuit to the given truth table. Unlike previous methods, this method does not necessarily require a correct initial circuit to improve it. It can start from a correct circuit or a near-correct circuit or even from an empty circuit, and tries to get a circuit that is better than the initial circuit. It can also achieve different circuits in different runs that are better than the initial circuit. Finally, from the various circuits that this algorithm has produced in different runs, the best is selected as the final circuit. The proposed algorithm also tries to produce a circuit as simple as possible with respect to don’t-care combinations. Also, the current algorithm does not depend on the type of gates. Any library, including arbitrary reversible gates, can be used in this method.
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References
Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183–91 (1961)
Saeedi, M., Zamani, M.S., Sedighi, M., Sasanian, Z.: Reversible circuit synthesis using a cycle-based approach. ACM JETC 6(4), 13 (2010)
Bhagyalakshmi, H.R., Venkatesha, M.K.: An improved design of a multiplier using reversible logic gates. Int. J. Eng. Sci. Technol. 2(8), 3838–45 (2010)
Miller, D.M., Maslov, D., Dueck, G.W.: A transformation based algorithm for reversible logic synthesis. In: Proceedings 2003. Design Automation Conference (IEEE Cat. No. 03CH37451) 2003 Jun 2. IEEE, pp. 318–323
Sasanian, Z., Saeedi, M., Sedighi, M., Zamani, M.S.: A cycle-based synthesis algorithm for reversible logic. In: Proceedings of the 2009 Asia and South Pacific Design Automation Conference 2009 Jan 19. IEEE Press, pp. 745–750
Datta, K., Gokhale, A., Sengupta, I., Rahaman, H.: An ESOP-based reversible circuit synthesis flow using simulated annealing. In: Applied Computation and Security Systems 2015. Springer, New Delhi, pp. 131–144
Abdessaied, N., Soeken, M., Dueck, G.W., Drechsler, R.: Reversible circuit rewriting with simulated annealing. In: 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) 2015 Oct 5. IEEE, pp. 286–291
Mohammadi, M., Eshghi, M.: Heuristic methods to use don’t cares in automated design of reversible and quantum logic circuits. Quantum Inf. Process. 7(4), 175–92 (2008)
Yanofsky, N.S., Mannucci, M.A.: Quantum Computing for Computer Scientists. Cambridge University Press, Cambridge (2008)
Nielsen, M.A., Chuang, I.: Quantum Computation and Quantum Information. Cambridge University Press, New York (2002)
Barenco, A., Bennett, C.H., Cleve, R., DiVincenzo, D.P., Margolus, N., Shor, P., Sleator, T., Smolin, J.A., Weinfurter, H.: Elementary gates for quantum computation. Phys. Rev. A 52(5), 3457 (1995)
Jamal, L., Shamsujjoha, M., Babu, H.H.: Design of optimal reversible carry look-ahead adder with optimal garbage and quantum cost. Int. J. Eng. Technol. 2(1), 44–50 (2012)
Lee, S., Lee, S.J., Kim, T., Lee, J.S., Biamonte, J., Perkowski, M.: The cost of quantum gate primitives. J. Multiple Valued Log. Soft Comput. 1, 12 (2006)
Mohammadi, M., Eshghi, M.: On figures of merit in reversible and quantum logic designs. Quantum Inf. Process. 8(4), 297–318 (2009)
Maslov, D., Dueck, G.W.: Improved quantum cost for n-bit Toffoli gates. Electron. Lett. 39(25), 1790–1 (2003)
Osman, M., Younes, A., Ismail, G., Farouk, R.: An improved design of n-bit universal reversible gate library. Int. J. Theor. Phys. 58, 25311–2549 (2019)
Monfared, A.T., Haghparast, M., Datta, K.: Quaternary quantum/reversible half-adder, full-adder, parallel adder and parallel adder/subtractor circuits. Int. J. Theor. Phys. 58, 2184–2199 (2019)
Gaur, H.M., Singh, A.K., Ghanekar, U.: Simplification and modification of multiple controlled Toffoli circuits for testability. J. Comput. Electron. 18(1), 356–63 (2019)
Saeedi, M., Markov, I.L.: Synthesis and optimization of reversible circuits–a survey. ACM CSUR 45(2), 21 (2013)
Shende, V.V., Prasad, A.K., Markov, I.L., Hayes, J.P.: Synthesis of reversible logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6), 710–22 (2003)
Golubitsky, O., Falconer, S.M., Maslov, D.: Synthesis of the optimal 4-bit reversible circuits. In: Design Automation Conference 2010 Jun 13. IEEE, pp. 653–656
Tara, N., Babu, H.M.: Synthesis of reversible PLA using products sharing. J. Comput. Electron. 15(2), 420–8 (2016)
Zhu, W., Li, Z., Zhang, G., Pan, S., Zhang, W.: A reversible logical circuit synthesis algorithm based on decomposition of cycle representations of permutations. Int. J. Theor. Phys. 57(8), 2466–74 (2018)
Li, Z., Chen, S., Song, X., Perkowski, M., Chen, H., Zhu, W.: Quantum circuit synthesis using a new quantum logic gate library of NCV quantum gates. Int. J. Theor. Phys. 56(4), 1023–38 (2017)
Van Laarhoven, P.J., Aarts, E.H.: Simulated annealing. In: Simulated Annealing: Theory and Applications. Springer, Dordrecht, pp. 7–15 (1987)
Kirkpatrick, S., Gelatt, C.D., Vecchi, M.P.: Optimization by simulated annealing. Science 220(4598), 671–80 (1983)
Wille, R., Große, D., Dueck, G.W., Drechsler, R.: Reversible logic synthesis with output permutation. In: 2009 22nd International Conference on VLSI Design 2009 Jan 5. IEEE, pp. 189–194
Maslov, D., Dueck, G.W., Miller, D.M., Negrevergne, C.: Quantum circuit simplification and level compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3), 436–44 (2008)
Szyprowski, M., Kerntopf, P.: Reducing quantum cost in reversible Toffoli circuits. arXiv preprint arXiv:1105.5831. 2011 May 29
Maslov, D., Dueck, G.W., Miller, D.M.: Fredkin/Toffoli templates for reversible logic synthesis. In: Proceedings of the 2003 IEEE/ACM International Conference on Computer-Aided Design 2003 Nov 9. IEEE Computer Society, p. 256
Maslov, D., Dueck, G.W., Miller, D.M.: Synthesis of Fredkin–Toffoli reversible networks. IEEE Trans. VLSI Syst. 13(6), 765-9 (2005)
Maslov, D.A.: Reversible Logic Synthesis. Doctoral dissertation, University of New Brunswick, Faculty of Computer Science
Arabzadeh, M., Saeedi, M.: RCViewer+: a viewer/analyzer for reversible and quantum circuits (2018)
Abubakar, M.Y., Jung, L.T., Zakaria, N., Younes, A., Abdel-Aty, A.H.: Reversible circuit synthesis by genetic programming using dynamic gate libraries. Quantum Inf. Process. 16(6), 160 (2017)
Miller, D.M., Dueck, G.W., Maslov, D.: A synthesis method for MVL reversible logic [multiple value logic]. In: Proceedings of 34th International Symposium on Multiple-Valued Logic 2004 May 22. IEEE, pp. 74–80
Younes, A.: Synthesis and optimization of reversible circuits for homogeneous Boolean functions. arXiv preprint arXiv:0710.0664. (2007)
Zakablukov, D.V.: Application of permutation group theory in reversible logic synthesis. In: International Conference on Reversible Computation Jul 7. Springer, Cham, pp. 223–238 (2016)
Maslov, D., Dueck, G.W., Miller, D.M.: Toffoli network synthesis with templates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6), 807–17 (2005)
Maslov, D., Miller, D.M., Dueck, G.W.: Templates for reversible circuit simplification. In: PACRIM 2005 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2005. 2005 Aug 24. IEEE, pp. 609–612
Golubitsky, O., Maslov, D.: A study of optimal 4-bit reversible Toffoli circuits and their synthesis. IEEE Trans. Comput. 61(9), 1341–53 (2011)
Dueck, G.W., Maslov, D.: Reversible function synthesis with minimum garbage outputs. In: 6th International Symposium on Representations and Methodology of Future Computing Technologies 2003 Mar 10, pp. 154–161
Miller, D.M., Dueck, G.W.: Spectral techniques for reversible logic synthesis. In: 6th International Symposium on Representations and Methodology of Future Computing Technologies 2003 Mar 10, pp. 56–62
Markov, I.: Book Review: A physical-design picture book. IEEE Des. Test Comput. 26(4), 100–1 (2009)
Szyprowski, M., Kerntopf, P.: An approach to quantum cost optimization in reversible circuits. In: 2011 11th IEEE International Conference on Nanotechnology 2011 Aug 15. IEEE, pp. 1521–1526
Wang, X., Jiao, L., Li, Y., Qi, Y., Wu, J.: A variable-length chromosome evolutionary algorithm for reversible circuit synthesis. J. Multiple Valued Log. Soft Comput. 25(6), 643–671 (2015)
Cheung, D., Maslov, D., Mathew, J., Pradhan, D.K.: On the design and optimization of a quantum polynomial-time attack on elliptic curve cryptography. In: Workshop on Quantum Computation, Communication, and Cryptography. Springer, Berlin, Heidelberg, pp. 96–104 (2008)
Maslov, D., Mathew, J., Cheung, D., Pradhan, D.K.: An O (m 2)-depth quantum algorithm for the elliptic curve discrete logarithm problem over GF (2 m) a. Quantum Inf. Comput. 9(7), 610–21 (2009)
Takahashi, Y., Tani, S., Kunihiro, N.: Quantum addition circuits and unbounded fan-out. arXiv preprint arXiv:0910.2530 (2009)
Feynman, R.P.: Quantum mechanical computers. Found. Phys. 16(6), 507–31 (1986)
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Shahidi, S.M., Etemadi Borujeni, S. A new method for reversible circuit synthesis using a Simulated Annealing algorithm and don’t-cares. J Comput Electron 20, 718–734 (2021). https://doi.org/10.1007/s10825-020-01620-4
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DOI: https://doi.org/10.1007/s10825-020-01620-4