Abstract
Reversible logic is a computing design, where the ideal implementation would produce zero entropy gain. This unique feature causes prominent use of reversible computing. At the same time, more integration capability and regular structure for synthesizing large number of logic functions made programmable devices enthusiastic to use. In this paper, we propose design algorithm of one of the programmable logic devices, Programmable Logic Array (PLA) with a newly designed low cost 3 \(\times \) 3 reversible Tara Babu (TB) gate, which can realize multi-output Exclusive-OR Sum of Product (ESOP) functions. In addition, we present a heuristic algorithm to sort and realize the product terms of ESOP functions in order to share the internal sub-products to reduce the number of gates in the proposed circuit. Proposed algorithms make the design more efficient with improvement 9.83 % in number of gates, 21.3 % in garbage outputs count and 14.75 % quantum cost parameters than the existing techniques averagely. Moreover, the area and power consumption of the proposed PLA are shown. Performance is also analyzed by using MCNC benchmark functions.
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References
Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183–191 (1961)
Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973)
Schrom, G., Selberherr, S.: Ultra-low-power cmos technology. In: Semiconductor Conference, Romania (2002)
Knill, E., Laamme, R., Milburn, G.J.: A scheme for eficient quantum computation with linear optics. Nature 409, 46–52 (2001)
Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Information. Cambridge University Press, Cambridge (2010)
Merkle, R.C.: Two types of mechanical reversible logic. Nanotechnology 4(2), 114–131 (1993)
Fleisher, H., Maissel, L.I.: An introduction to array logic. IBM J. Res. Dev. 19(2), 98–109 (1975)
Sasao, T.: Exmin2: A simplification algorithm for exclusive-or-sum-of-products expressions for multiple-valued input two-valued output functions. IEEE Trans Comput Aided Des Integr Circuits Syst 12(5), 621–632 (1993)
Mishchenko, A., Perkowski, M.: Logic synthesis of reversible wave cascades. In: International Workshop on Logic Synthesis, pp. 197–202 (2002)
Perkowski, M., Kerntof, A.B.P., et al.: Regularity and symmetry as a base of efficient realization of reversible logic circuits. In: International Workshop on Logic, Synthesis, pp. 245–252 (2001)
Maslov, D., Dueck, G.: Reversible cascades with minimal garbage. IEEE Trans. CAD 23(11), 1497–1509 (2004)
Chowdhury, A.R., Nazmul, R., Babu, H.M.H.: A new approach to synthesize multiple-output functions using reversible programmable logic arrays. IEEE 19rd International Conference on VLSI Design, pp. 311–316. Hyderabad (2006)
Rahman, R., Jamal, L., Babu, H.M.H.: Design of reversible fault tolerant programmable logic arrays with vector orientation. Int. J. Inf. Commun. Technol. Res. 337–342 (2011)
Mitra, S.K., Jamal, L., Kaneko, Mineo, Babu, H.M.H.: Design and minimization of reversible programmable logic arrays. Proceedings of Symposium on VLSI, GLSVLSI ’12, NY, pp. 215–220 (2012)
CMOS 45 nm Open Cell Library, http://www.si2.org/openeda.si2.org/projects/nangatelib (Last visited April 2015)
DSCH2: Microwind and dsch information page, Available at, http://www.microwind.org. (Last visited April, 2015)
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We would like to thank the ministry of ICT of Government of the People’s Republic of Bangladesh for the innovation fund of research.
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Tara, N., Babu, H.M.H. Synthesis of reversible PLA using products sharing. J Comput Electron 15, 420–428 (2016). https://doi.org/10.1007/s10825-015-0762-5
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DOI: https://doi.org/10.1007/s10825-015-0762-5