Abstract
Tunneling field-effect transistor (TFET) suffers from ultra-sharp doping concentration gradients in both the source/channel junction and drain/channel junction. Recently, the junctionless (JL) TFET device has been proposed to avoid the issue of ultra-sharp doping concentration gradients. Employing III–V semiconductor as a drain/channel material and a group IV semiconductor as a source material has been proposed to improve the heterojunctionless (HJL) TFET device performance. GaAs:Ge HJL-TFET has proved more efficient than other HJL-TFET structures in providing more ON-state current, less OFF-state current, and less subthreshold slope (SS). For the first time in this paper, GaSb as the source material and GaAs as the drain/channel material have been proposed. This is the so-called GaAs:GaSb HJL-TFET structure. Simulation results show that the GaAs:GaSb HJL-TFET provides improvement in both \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio and SS as compared to GaAs:Ge HJL-TFETs. We demonstrate that for a 20 nm channel length, the GaAs:GaSb HJL-TFET average SS is improved by 19% and the point slope by 52%, as compared to those of the GaAs:Ge HJL-TFET. Numerical simulations show that the average SS and \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio of GaAs:GaSb HJL-TFET are nearly 9 mV/dec and 3E12, respectively, for a 10 nm channel length. Thus, the GaAs:GaSb HJL-TFET holds promise for future logic transistor applications.
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References
Bo, Y., Wang, L., Yu, Y., Asbeck, P.M., Yuan, T.: Scaling of nanowire transistors. IEEE Trans. Electron Devices 55, 2846–2858 (2008)
Park, P.S., Rajan, S.: Simulation of short-channel effects in N- and Ga-Polar AlGaN/GaN HEMTs. IEEE Trans. Electron Devices 58, 704–708 (2011)
Joshi, G., Choudhary, A.: Analysis of short channel effects in nanoscale MOSFETs. Int. J. Nanosci. 10, 275–278 (2011)
Vadizadeh, M.: Improving gate delay and ION/IOFF in nanoscale heterostructure field effect diode (H-FED) by using heavy doped layers in the channel. Appl. Phys. A 122, 1–9 (2016)
Loan, S.A., Qureshi, S., Iyer, S.S.K.: A novel partial-ground-plane- based MOSFET on selective buried oxide: 2-D simulation study. IEEE Trans. Electron Device Lett. 57, 671–680 (2010)
Kuhn, K.J.: Considerations for ultimate CMOS scaling. IEEE Trans. Electron Device Lett. 59, 1813–1828 (2012)
Yan, R., Duane, R., Razavi, P., Afzalian, A., Ferain, I., Lee, C.W., Akhavan, N.D., Nguyen, B.Y., Bourdelle, K.K., Colinge, J.P.: LDD and back-gate engineering for fully depleted planar SOI transistors with thin buried oxide. IEEE Trans. Electron Devices 57, 1319–1326 (2010)
Vadizadeh, M., Fathipour, M., Darvish, G.H.: Silicon on raised insulator field effect diode (SORI-FED) for alleviating scaling problem in FED. Int. J. Mod. Phys. B 28, 450038 (2014)
Crupi, F., Albano, D., Alioto, M., Franco, J., Selmi, L., Mitard, J., Groeseneken, G.: Impact of high-mobility materials on the performance of near- and sub-threshold CMOS logic circuits. IEEE Trans. Electron Devices 60, 972–977 (2013)
Vadizadeh, M., Fathipour, M.: Using low-k oxide for reduction of leakage current in Double Gate Tunnel FET. In: ULIS2009: 10th International Conference on Ultimate Integration of Silicon, Aachen, March, pp. 301–304 (2009)
Colinge, J.P., Lee, C.W., Afzalian, A., Akhavan, N.D., Yan, R., Ferain, I., Razavi, P., O’neill, B., Blake, A., White, M., Kelleher, A.M.: Nanowire transistors without junctions. Nat. Nanotechnol. 5, 225–229 (2010)
Rudenko, T., Nazarov, A., Yu, R., Barraud, S., Cherkaoui, K., Razavi, P., Fagas, G.: Electron mobility in heavily doped junctionless nanowire SOI MOSFETs. Microelectron. Eng. 109, 326–329 (2013)
Akhavan, N.D., Ferain, I., Razavi, P., Yu, R., Colinge, J.-P.: Improvement of carrier ballisticity in junctionless nanowire transistors. Appl. Phys. Lett. 98, 103510–1 (2011)
Lee, C.-W., Ferain, I., Afzalian, A., Yan, R., Akhavan, N.D., Razavi, P., Colinge, J.-P.: Performance estimation of junctionless multigate transistors. Solid State Electron. 54, 97–103 (2010)
Singh, P., Singh, N., Miao, J., Park, W.-T., Kwong, D.-L.: Gate-all-around junctionless nanowire MOSFET with improved low-frequency noise behavior. IEEE Electron Device Lett. 32, 1752–1754 (2011)
Ghosh, Bahniman, Mondal, Partha, Akram, M.W., Bal, Punyasloka, Akshay, Kumar Salimath: Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime. J. Semicond. 35, 064001 (2014)
Rios, R., Cappellani, A., Armstrong, M., Budrevich, A., Gomez, H., Pai, R., Rahhal-orabi, N., Kuhn, K.: Comparison of junctionless and conventional trigate transistors with \(L_g\) down to 26 nm. IEEE Electron Device Lett. 32, 1170–1172 (2011)
Dehdashti Akhavan, N., Ferain, I., Razavi, P., Yu, R., Colinge, J.P.: Improvement of carrier ballisticity in junctionless nanowire transistors. Appl. Phys. Lett. 98, 103510 (2011)
Akhavan, N.D., Ferain, I., Yu, R., Razavi, P., Colinge, J.P.: Emission and absorption of optical phonons in multigate silicon nanowire MOSFETs. J. Comput. Electron. 11, 249–265 (2012)
Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-\(\kappa \) gate dielectric. IEEE Trans. Electron Devices 54, 1725–1733 (2007)
Nirschl, T., Fischer, J., Fulde, M., Bargagli-Stoffi, A., Sterkel, M., Sedlmeir, J., Weber, C., Heinrich, R., Schaper, U., Einfeld, J., Neubert, R.: Scaling properties of the tunneling field effect transistor (TFET): device and circuit. Solid-State Electron. 50, 44–51 (2006)
Kumar, S.B., Seol, G., Guo, J.: Modeling of a vertical tunneling graphene heterojunction field-effect transistor. J. Appl. Phys. Lett. 101, 033503 (2012)
Ghoreishi, S.S., Saghafi, K., Yousefi, R., Moravvej-farshi, M.K.: A novel tunneling graphene nano ribbon field effect transistor with dual material gate: numerical studies. Superlattices Microstruct. 97, 277–286 (2016)
Kazazis, D., Jannaty, P., Zaslavsky, A., Le Royer, C., Tabone, C., Clavelier, L., Cristoloveanu, S.: Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator. Appl. Phys. Lett. 94, 263508 (2009)
Toh, E.H., Wang, G.H., Lo, G.Q., Chan, L., Samudra, G., Yeo, Y.C.: Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction. Appl. Phys. Lett. 90, 023505 (2007)
Ghosh, B., Akram, M.W.: Junctionless tunnel field effect transistor. IEEE Electron. Dev. Lett. 34, 584–586 (2013)
Ghosh, B., Bal, P., Mondal, P.: A junctionless tunnel field effect transistor with low subthreshold slope. J. Comput. Electron. 12, 428–436 (2013)
Asthana, P.K., Ghosh, B., Goswami, Y., Tripathi, B.M.: High-speed and low-power ultradeep-submicrometer III–V heterojunctionless tunnel field-effect transistor. IEEE Trans. Electron Devices 61, 479–486 (2014)
Palestri, P., De Michielis Michielis, L., Iellina, M. Selmi: Challenges in the introduction of band to band tunneling in semiclassical models for tunnel-FETs (2013). http://www.steeper-project.org/resources/Dissemination/Workshops/Sispad2010_Workshop/talk8_Palestri.pdf
ATLAS User’s Manual (2013). http://www.silvaco.com
Schenk, A.: A model for the field and temperature dependence of SRH lifetimes in silicon. Solid-State Electron. 35, 1585–1596 (1992)
Hansch, W., Vogelsang, T., Kirchner, R., Orlowski, M.: Carrier transport near the Si/SiO\(_2\) interface of a MOSFET. Solid-State Electron. 32, 839–849 (1989)
Slotboom, J.W., de Graaff, H.: Measurements of bandgap narrowing in Si bipolar transistors. Solid-State Electron. 19, 857–862 (1976)
Chau, Robert, Suman, Datta, Mark, Doczy, Brian, Doyle, Ben, Jin, Jack, Kavalieros, Amlan, Majumdar, Matthew, Metz, Marko, Radosavljevic: Benchmarking nanotechnology for high-performance and low-power logic transistor applications. IEEE Trans. Nanotechnol. 4, 153–158 (2005)
Kumar, M.P.V., Hu, C.Y., Kao, K.H., Lee, Y.J., Chao, T.S.: Impacts of the shell doping profile on the electrical characteristics of junctionless FETs. IEEE Trans. Electron Devices 62, 3541–3546 (2015)
Tornberg, M., Mårtensson, E.K., Zamani, R.R., Lehmann, S., Dick, K.A., Ghalamestani, S.G.: Demonstration of Sn-seeded GaSb homo-and GaAs-GaSb heterostructural nanowires. Nanotechnology 27, 175602 (2016)
Shi, S., Zhang, Z., Lu, Z., Shu, H., Chen, P., Li, N., Zou, J., Lu, W.: Evolution of morphology and microstructure of GaAs/GaSb nanowire heterostructures. Nanoscale Res. Lett. 10, 108 (2015)
Parisini, A., Baldini, M., Gombia, E., Frigeri, C., Jakomin, R., Tarricone, L.: Electrical and interfacial properties of GaAs/GaSb metal-organic vapour phase epitaxy heterostructures. J. Appl. Phys. 113, 043719 (2013)
Ye, P.D., Wilk, G.D., Kwo, J., Yang, B.A.Y.B., Gossmann, H.J., Frei, M.A.F.M., Chu, S.N.G., Mannaerts, J.P., Sergent, M.A.S.M., Hong, M.A.H.M., Ng, K.K.: GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition. IEEE Electron Device Lett. 24, 209–211 (2003)
Kumar, M.Jagadesh, Janardhanan, Sindhu: Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Devices 60, 3285–3290 (2013)
Ranade, P., Takeuchi, H., King, T.-J., Hu, C.: Work function engineering of molybdenum gate electrodes by nitrogen implantation. Electrochem. Solid-State Lett. 4, G85–G87 (2001)
Bessire, Cedric D., Björk, Mikael T., Schmid, Heinz, Schenk, Andreas, Reuter, Kathleen B., Riel, Heike: Trap-assisted tunneling in Si-InAs nanowire heterojunction tunnel diodes’. Nano Lett. 11, 4195–4199 (2011)
Khayer, M.Abul, Lake, Roger K.: Effects of band-tails on the subthreshold characteristics of nanowire band-to-band tunneling transistors. J. Appl. Phys. 110, 074508 (2011)
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Vadizadeh, M. Characteristics of GaAs/GaSb tunnel field-effect transistors without doping junctions: numerical studies. J Comput Electron 17, 745–755 (2018). https://doi.org/10.1007/s10825-018-1136-6
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DOI: https://doi.org/10.1007/s10825-018-1136-6