Abstract
This paper presents the analytical approximation of device physics of heterojunction based double gate (DG) Tunnel field effect transistors (TFETs) in terms of potential distribution, electron density and electron barrier tunneling. In order to improve the device performance with respect to ON current (ION), DG TFET with gate-drain overlap is developed. An asymmetric gate oxide is introduced in the gate - drain overlap region and is compared to DG TFET. The device physics and its performance characteristics are studied by using various materials, such as Si, SiGe, InAs and GaSb. The simulated results are validated against the model values. DG TFETs with gate-drain overlap offers higher tunneling probability compared to DG TFETs. Also GaSb/Si based DG TFETs with gate-drain overlap shows good performance improvement by offering higher tunneling probability which in turn offers a higher ION of 1.15 mA/μm.
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S. Poorvasha and B. Lakshmi have contributed to the design and implementation of the research, to the analysis of the results and to the writing of the manuscript.
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Poorvasha, S., Lakshmi, B. Investigation of the Device Electrical Parameters for Homo and Hetero Junction Based TFETs. Silicon 14, 1479–1488 (2022). https://doi.org/10.1007/s12633-020-00934-z
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DOI: https://doi.org/10.1007/s12633-020-00934-z