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A circuit-level methodology for leakage power reduction of high-efficient compressors in 22-nm CMOS technology

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Abstract

A new circuit-level methodology called input controlled leakage restrainer transistor (ICLRT) compatible with single threshold CMOS technology is proposed in this paper, to further discount the leakage and short-circuit powers. To implement this idea a PMOS ICLRT is placed on top of the PUN and an NMOS ICLRT is located at the bottom of the PDN for any path from the supply voltage and the ground to output. The ICLRTs can be deliberately applied to the main sources of leakage and short-circuit currents to reduce total power dissipation. To test the proposed technique, ICLRTs are applied to four 4-2 CMOS compressors. The efficiency of the proposed methodology is evaluated using SPICE simulations in 22-nm BSIM4 (level-54 parameters) CMOS technology. Simulation results with 0.9-V power supply revealed that the power consumption of the 4-2 CMOS compressors based on ICLRT technique is reduced 59.62–74.28% and also power-delay product (PDP) is diminished 32–46.78% relative to corresponding original designs.

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Data availability

The datasets generated and analyzed during the current study are available from the corresponding author on reasonable request.

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Authors and Affiliations

  1. Department of Electrical and Electronics Engineering, Iran University of Science and Technology (IUST), Tehran, Iran

    Mohammad Moradinezhad Maryan, Seyed Javad Azhari & Majid Amini-Valashani

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  1. Mohammad Moradinezhad Maryan
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  2. Seyed Javad Azhari
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  3. Majid Amini-Valashani
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Correspondence to Mohammad Moradinezhad Maryan.

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Maryan, M.M., Azhari, S.J. & Amini-Valashani, M. A circuit-level methodology for leakage power reduction of high-efficient compressors in 22-nm CMOS technology. Analog Integr Circ Sig Process 110, 569–581 (2022). https://doi.org/10.1007/s10470-021-01983-z

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  • DOI: https://doi.org/10.1007/s10470-021-01983-z

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