Abstract
This paper presents the first aggressively calibrated 14-b 32 MS/s pipelined ADC. The design uses a comprehensive digital background calibration engine that compensates for linear and nonlinear errors as well as capacitor mismatch in multi-bit DAC. Background calibration techniques that estimate the errors by correlating the output of ADC with the calibration signal have a very slow convergence rate. This paper also presents a fully digital technique to speed up the convergence in the error estimation procedure. By digitally filtering the input signal during the error estimation, the convergence rate of the calibration has been improved significantly. Implemented in TSMC 0.25 μm technology, the pipelined ADC consumes 75 mA from 2.5 V and occupies 2.8 mm2 of active area. Measurement results show that calibration significantly improved dynamic (SNDR, SFDR) as well as static (DNL, INL) performance of the ADC.
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Notes
In this design, the multi-bit stages have two bits effective resolution with one full bit redundancy used for calibration. Therefore, eight comparators per stage are used although the gain of each stage is only four.
In this design, each stage has an effective resolution of two bits and one full bit redundancy is considered for calibration purposes.
References
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Acknowledgement
The authors thank Dana Price and Doug Garrity from Freescale, Tempe, AZ for useful suggestions and help with the testing and Connection One Center at ASU for supporting this project.
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Jalali-Farahani, B., Meruva, A. A 14-b 32 MS/s pipelined ADC with fast convergence comprehensive background calibration. Analog Integr Circ Sig Process 61, 65–74 (2009). https://doi.org/10.1007/s10470-008-9278-2
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DOI: https://doi.org/10.1007/s10470-008-9278-2