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Vaq-Assisted Low-Power Capacitor-Splitting Switching Scheme for SAR ADCs

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Abstract

In this paper, a novel four-level capacitor-splitting switching scheme for successive approximation register analog-to-digital converters is proposed. The fourth reference voltage Vaq, equal to VREF/4, is introduced during the last bit-cycle to optimize capacitor area and power consumption. So, for a 10-bit SAR ADC, the capacitor area is reduced by 75%, and average switching energy of − 5.4 CVREF2 is achieved, which is 102.11% less than the monotonic switching method. The common-mode voltage remains at VREF/2 except for the last two bit-cycles. 1% capacitor mismatch leads to root-mean-square (RMS) values of 0.321 LSB for DNL and INL. Inaccuracy of VCM/Vaq has little effect on the accuracy of the SAR ADC. Vaq control logic is easier to design than those of other reference voltages. As a result, the proposed switching scheme offers a better trade-off between energy efficiency, capacitor saving, common-mode voltage variation, logic complexity, and accuracy. A 0.6-V 10-bit 20 KS/s SAR ADC in 0.18-μm 1P6M CMOS technology is designed, occupying an area of about 340 × 380 μm2. The SAR ADC with Nyquist rate input has ENOB, SNDR, and SFDR values of 9.57 bits, 59.41 dB, and 70.56 dB, respectively. It consumes 35.1 nW, resulting in a figure-of-merit (FoM) of 2.31 fJ/conversion-step.

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Authors and Affiliations

  1. School of Electronic, Electrical Engineering, and Physics, Fujian University of Technology, Fuzhou, China

    Hao Wang

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  1. Hao Wang
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Wang, H. Vaq-Assisted Low-Power Capacitor-Splitting Switching Scheme for SAR ADCs. Circuits Syst Signal Process 41, 6615–6631 (2022). https://doi.org/10.1007/s00034-022-02097-1

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  • DOI: https://doi.org/10.1007/s00034-022-02097-1

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