Abstract
The parer illustrates a new efficient FPGA hardware architecture for the Active Zero State Pulse Width Modulation, which exploits the Taylor Series to decompose the dwell-times expressions. This decomposition avoids further resources, like external reference signals or Digital Signal Processor, as well as specific architectures, like CORDIC core or Look Up Table-based approaches, which are all solutions provided by the state of the art. All the calculations are done by a fixed-point Arithmetic Logic Unit, which can perform a real time variation of the output amplitude.
The architecture has been implemented on a Xilinx Artix VII FPGA XC7A35T1CPG236C requiring 1973 LUTs and 501 Flip Flops, respectively, the \(9.49\%\) and \(1.20\%\) of the overall resources, and a dynamic power consumption of 1 \(\textrm{mW}\).
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
Li, X., et al.: High-voltage hybrid igbt power modules for miniaturization of rolling stock traction inverters. IEEE Trans. Industr. Electron. 69(2), 1266–1275 (2022)
Di Benedetto, L., Licciardo, G., Erlbacher, T., Bauer, A., Rubino, A.: Optimized design for 4h-sic power dmosfet. IEEE Electron Device Lett. 37(11), 1454–1457 (2016)
Di Benedetto, L., Licciardo, G.D., Erlbacher, T., Bauer, A.J., Liguori, R., Rubino, A.: A model of electric field distribution in gate oxide and jfet-region of 4h-sic dmosfets. IEEE Trans. Electron Devices 63(9), 3795–3799 (2016)
Barth, C.B., et al.: Design, operation, and loss characterization of a 1-kw gan-based three-level converter at cryogenic temperatures. IEEE Trans. Power Electron. 35(11), 12040–12052 (2020)
Naradhipa, A.M., Kim, S., Yang, D., Choi, S., Yeo, I., Lee, Y.: Power density optimization of 700 khz gan-based auxiliary power module for electric vehicles. IEEE Trans. Power Electron. 36(5), 5610–5621 (2020)
Henn, J., et al.: Intelligent gate drivers for future power converters. IEEE Trans. Power Electron. 37(3), 3484–3503 (2021)
Ruiz, G.E.M., Muñoz, N., Cano, J.B.: Design methodologies and programmable devices used in power electronic converters-a survey. In: IEEE Workshop on Power Electronics and Power Quality Applications (PEPQA), vol. 2015, pp. 1–6. IEEE (2015)
Pop, O., Chindris, G., Dulf, A.: Using dsp technology for true sine pwm generators for power inverters. In: 27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004, vol. 1, pp. 141–146. IEEE (2004)
Monmasson, E., Idkhajine, L., Bahri, I., Charaabi, L., et al.: Design methodology and fpga-based controllers for power electronics and drive applications. In: 2010 5th IEEE Conference on Industrial Electronics and Applications, pp. 2328–2338. IEEE (2010)
Rashid, M.H.: Power electronics handbook: devices, circuits and applications. Elsevier (2010)
m-Mode SVPWM Technique for Power Converters. CPES. Springer, Singapore (2019). https://doi.org/10.1007/978-981-13-1382-0_9
Wiśniewski, R., Bazydło, G., Szcześniak, P.: Svm algorithm oriented for implementation in a low-cost xilinx fpga. Integration 64, 163–172 (2019)
Shreyas, S.G., Vachhani, L.: Area efficient reconfigurable architecture for current control loop of a servo controller. In: 2012 IEEE 7th International Conference on Industrial and Information Systems (ICIIS), pp. 1–6 (2012)
Tzou, Y.Y., Hsu, H.J.: Fpga realization of space-vector pwm control ic for three-phase pwm inverters. IEEE Trans. Power Electron. 12(6), 953–963 (1997). https://doi.org/10.1109/63.641493
Neacu, D.O., Kim, J.C., Lehman, B.: A three-phase multioptimal pwm implemented on 2-gbit flash memory integrated circuits. IEEE Trans. Power Electron. 32(7), 5813–5826 (2017)
Neacsu, D.O.: Novel microcontrollers with direct access to flash memory benefit implementation of multi-optimal space vector modulation. IEEE Trans. Industr. Inf. 8(3), 528–535 (2012)
Donisi, A., Di Benedetto, L., Licciardo, G.D., Rubino, A., Piccirilli, E., Lanzotti, E.: A fully fpga implementation of svpwm for three-phase inverters without external reference signals. In: 2020 IEEE International Conference on Environment and Electrical Engineering and 2020 IEEE Industrial and Commercial Power Systems Europe (EEEIC / I CPS Europe), pp. 1–5 (2020)
Donisi, A., Di Benedetto, L., Licciardo, G.D., Rubino, A., Piccirilli, E., Lanzotti, E.: Design of digital controller for svpwm algorithm with real-time control of the output amplitude and switching frequency. In: 2021 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5 (2021)
Di Benedetto, L., Donisi, A., Licciardo, G.D., Rubino, A.: A hardware architecture for svpwm digital control with variable carrier frequency and amplitude. IEEE Trans. Industrial Informat. (2021)
Di Benedetto, L., et al.: Implementation of hardware architecture for svpwm with arbitrary parameters. IEEE Access 10, 32381–32393 (2022)
Ali, S.M., Reddy, V.V., Kalavathi, M.S.: Simplified active zero state pwm algorithms for vector controlled induction motor drives for reduced common mode voltage. In: International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), pp, 1–7 (2014)
Hou, C.C., Shih, C.C., Cheng, P.T., Hava, A.M.: Common-mode voltage reduction pulsewidth modulation techniques for three-phase grid-connected converters. IEEE Trans. Power Electron. 28(4), 1971–1979 (2012)
Lai, Y.S., Chen, P.S., Lee, H.K., Chou, J.: Optimal common-mode voltage reduction pwm technique for inverter control with consideration of the dead-time effects-part ii: applications to im drives with diode front end. IEEE Trans. Ind. Appl. 40(6), 1613–1620 (2004)
In: Taylor expansions and applications, pp. 223–255. Springer Milan, Milano (2008)
Xilinx inc.: Artix 7. (2018). https://www.xilinx.com/products/silicon-devices/fpga/artix-7.html (Accessed 27 Feb 2018)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2023 The Author(s), under exclusive license to Springer Nature Switzerland AG
About this paper
Cite this paper
Donisi, A., Di Benedetto, L., Liguori, R., Licciardo, G.D., Rubino, A. (2023). A FPGA HardWare Architecture for AZSPWM Based on a Taylor Series Decomposition. In: Berta, R., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2022. Lecture Notes in Electrical Engineering, vol 1036. Springer, Cham. https://doi.org/10.1007/978-3-031-30333-3_10
Download citation
DOI: https://doi.org/10.1007/978-3-031-30333-3_10
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-031-30332-6
Online ISBN: 978-3-031-30333-3
eBook Packages: EngineeringEngineering (R0)