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Design and Implementation of Fractional Order Differintegrators Using Reduced s to z Transforms

  • DYNAMIC CHAOS IN RADIOPHYSICS AND ELECTRONICS
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Abstract

The Design and implementation of fractional order digital differentiators and integrators is the main objective of this paper. Identify the novel reduced s to z transforms calculated using model order reduction techniques. Thus the transforms are discretized directly using Continued Fraction Expansion (CFE).The designed differentiators and integrators are implemented on Xilinx Spartan 3E field programmable gate arrays (FPGA) and are tested using the sinusoidal, square and triangular waveforms. The practical results agree with the theoretical ones.

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ACKNOWLEDGMENTS

Authors wish to acknowledge the university authorities, Jawaharlal Nehru Technological University Kakinada (JNTUK), Kakinada, Andhra Pradesh, India, for providing facilities to carry out this research.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University Kakinada, 533003, Andhra Pradesh, India

    K. Rajasekhar & B. T. Krishna

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  1. K. Rajasekhar
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  2. B. T. Krishna
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Correspondence to K. Rajasekhar or B. T. Krishna.

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Rajasekhar, K., Krishna, B.T. Design and Implementation of Fractional Order Differintegrators Using Reduced s to z Transforms. J. Commun. Technol. Electron. 63, 1406–1417 (2018). https://doi.org/10.1134/S1064226918120185

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