1. Progressive and explicit refinement of scheduling for multidimensional data-flow applications using UML MARTE

   • Calin Glitia
   • Julien DeAntoni
   • Abdoulaye Gamatié

   OriginalPaper 02 August 2014 Pages: 1 - 33

   

2. Design methodology for on-chip-based processor debugger

   • Hyeongbae Park
   • Jingzhe Xu
   • Gyun Woo

   OriginalPaper 23 April 2014 Pages: 35 - 57

   

3. The fast evolving landscape of on-chip communication

   • Davide Bertozzi
   • Giorgos Dimitrakopoulos
   • Sören Sonntag

   OriginalPaper 30 April 2014 Pages: 59 - 76

4. LSB-Tree: a log-structured B-Tree index structure for NAND flash SSDs

   • Bo-kyeong Kim
   • Dong-Ho Lee

   OriginalPaper 21 June 2014 Pages: 77 - 100

   

5. Data pattern aware FTL for SLC+MLC hybrid SSD

   • Se Jin Kwon
   • Tae-Sun Chung

   OriginalPaper 24 May 2014 Pages: 101 - 127

   

6. Redundancy optimization for error recovery in digital microfluidic biochips

   • Mirela Alistar
   • Paul Pop
   • Jan Madsen

   OriginalPaper 13 January 2015 Pages: 129 - 159

   

7. Application-aware deduplication for performance improvement of flash memory

   • Joon-Young Paik
   • Tae-Sun Chung
   • Eun-Sun Cho

   OriginalPaper 27 September 2014 Pages: 161 - 188

   

8. Enabling FPGA routing configuration sharing in dynamic partial reconfiguration

   • Brahim Al Farisi
   • Karel Heyse
   • Dirk Stroobandt

   OriginalPaper 18 September 2014 Pages: 189 - 221