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Design methodology for on-chip-based processor debugger

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Abstract

Due to the increased complexity of modern embedded systems and time-to-market constraints, a debugger with efficient debugging functions is becoming increasingly necessary, and it plays an important role in the development of application systems. Accordingly, the implementation of efficient debug functionalities must a critical process in the design of a new processor. Since deeply embedded processor cores in a core-based system chip allow only restricted access for debugging its internal status, most recent processors employ the on-chip-based debug method that embeds special logic-supporting debug capabilities. In this paper, we propose an on-chip debug support logic that can be embedded into the processor core to support debug functions. Moreover, we describe an overall implementation method of the on-chip-based processor debugger based on the on-chip debug support logic, which includes a source-level debugger and an interface block. We designed an on-chip debug support logic, and embedded it into a target processor core. We used the GNU Project debugger (GDB) as the source-level debugger of the target processor core. An interface block that uses the remote debugging features of GDB was also developed and that includes a software module and a hardware board. We discuss all major design steps for implementing this on-chip-based processor debugger. We have successfully applied the proposed implementation method to develop the processor debugger for two new 32-bit RISC processors. In addition, we introduce another use of the on-chip-based processor debugger in the design of a processor-based system chip, which can facilitate simulation-based functional verification.

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References

  1. Zorian Yervant, Marinissen Erik Jan, Dey Sujit (1999) Testing embedded-core-based system chips. Computer 32(6):52–60. doi:10.1109/2.769444

    Article  Google Scholar 

  2. Hopkins Andrew BT, McDonald-Maier Klaus D (2006) Debug support strategy for systems-on-chips with multiple processor cores. IEEE Trans Comput 55(2):174–184. doi:10.1109/TC.2006.22

    Article  Google Scholar 

  3. ARM Ltd Embedded-ICE block specification. (2011)http://www.arm.com

  4. ARM Ltd ETM (embedded trace marcocell) block specification. (2011) http://www.arm.com

  5. MIPS Technologies Inc EJTAG trace control block specification. (2011) http://www.mips.com

  6. PDtrace\(^{\rm {TM}}\) Interface specification. (2011) http://www.mips.com

  7. RealView Development Suite. (2011) http://www.arm.com

  8. MicroBlaze Debug Module (MDM). (2011) http://www.xilinx.com

  9. System Navigator\(^{\rm {TM}}\) Probe. (2011) http://www.mips.com

  10. Vermeulen B, van Rootselaar GJ (2000) Silicon debug of a co-processor array for video applications. In: Fifth IEEE international high-level design validation and test workshop (HLDVT’00), p 47

  11. Vermeulen B, Oostdijk S, Bouwman F (2001) Test and debug strategy of the PNX8525 Nexperia\(^{\rm {TM}}\) digital video platform system chip. In: International test conference 2001 (ITC’01), p 121

  12. Vermeulen B, Waayers T, Goel SK (2002) Core-based scan architecture for silicon debug. In: Proceedings of IEEE international test conference, Washington, p 638

  13. Huang I-J, Kao C-F, Chen H-M, Juan C-N (2002) A retargetable embedded in-circuit emulation module for microprocessors. IEEE Des Test Comput 19(4):28–38

    Article  Google Scholar 

  14. Maier KD (2003) On-chip debug support for embedded systems-on-chip. In: ISCAS. Bangkok, Thailand, pp 565–568

  15. Leatherman R, Stollon N (2005) An embedded debugging architecture for SoCs. IEEE Potentials 24(1):12–16

    Article  Google Scholar 

  16. Vermeulen B (2008) Functional debug techniques for embedded systems. IEEE Des Test Comput 25(3):208–215

    Article  MathSciNet  Google Scholar 

  17. Stollon N et al. (2004) Multi-core embedded debug for structured ASIC systems. In: Proceedings of designcon

  18. Mayer A, Siebert H, McDonald-Maier KD (2007) Boosting debugging support for complex systems on chip. Computer 40(4):76–81

    Article  Google Scholar 

  19. Paulin PG, Santana M (2002) FlexWare: a retargetable embedded-software development environment. IEEE Des Test Comput 19(4):59–69

    Article  Google Scholar 

  20. Stallman R, Pesch R, Shebs S GDB user manual: debugging with GDB (the GNU source-Level debugger. GDB version 6.4. Technical report, Free Software Foundation, Cambridge

  21. IEEE Std 1149.1a-1993 (1993) Test access port and boundary-scan architecture. IEEE, Piscataway

  22. Hopkins, McDonald-Maier K (2006) Debug support for complex systems on-chip: a review. IEE Proc Comput Digit Tech 153(4):197–207

    Article  Google Scholar 

  23. Rosenberg JB (1996) How debuggers work-algorithms, data structures, and architecture. Wiley, New York

    Google Scholar 

  24. Hao H, Bhabuthmal K (1995) Clock controller design in superSPARCTMII microprocessor. In: Proceedings of international test conference on computer design (ICCD 95), pp 124–129

  25. Hao H, Avra R (1995) Structured design-for-debug: the superSPARCTMI1 methodology and implementation. In: Proceedings of international test conference (ITC 95), pp 175–183

  26. van Rootselaar GJ, Vermeulen B (1999) Silicon debug: scan chains alone are not enough. International test conference (ITC’99), p 892

  27. Emnett F, Biegel M (2000) Power reduction through RTL clock gating?. SNUG, San Jose

    Google Scholar 

  28. Vertext-5 user manual, (2011) p 105. http://www.xilinx.com

  29. Park H et al (2009) Design of on-chip debugging system using GNU debugger. IEEK 46(1):24–38

    Google Scholar 

  30. Alves GR, Martins Ferreira JM (1999) From design-for-test to design-for-debug-and-test: analysis of requirements and limitations for 1149.1. In: Proceedings of 17th IEEE VLSI test symposium (VTS99), IEEE CS Press, Los Alamitos, pp 473–480

  31. Gatliff B (1999) Embedding with GNU: GNU debugger. Red Hat Developer Network (RHDN)

  32. Gatliff B (1999) Embedding with GNU: The GDB remote serial protocol. Red Hat Developer Network (RHDN)

  33. Tan M (2002) A minimal GDB stub for embedded remote debugging. http://www1.cs.columbia.edu/~sedwards/classes/2002/w4995-02/tan-final.pdf

  34. Shebs S (2000) GDB: an open source debugger for embedded development. Red Hat

  35. Pizzi R (1993) GNU gdb internal architecture

  36. Gilmore J, Shebs S (2004) GDB internals, cygnus solutions. http://www.gnuarm.com/pdf/gdbint.pdf

  37. Bennett J (2008) Howto: porting the GNU debugger. Practical experience with the OpenRISC 1000 architecture. http://www.embecosm.com/download/ean3.html

  38. Open On-Chip Debugger. (2011) http://openocd.berlios.de/web/

  39. Xilinx Microprocessor Debugger (XMD). (2011) http://www.xilinx.com

  40. RealView ICE and RealView Trace User Guide. (2011) http://infocenter.arm.com/help/topic/com.arm.doc.dui0155g/DUI0155G_rvi_user_guide.pdf

  41. TRACE32 In-Circuit Debugger. (2011) http://www.lauterbach.de/tutorial.pdf

  42. S3C2410X 32-Bit RISC Microprocessor user’s manual. (2011) http://www.samsung.com/

  43. Questa Codelink. (2011) http://www.mentor.com/products/fv/codelink/

  44. Busonera G, Forin A (2007) eBug: debugging extensions for the eMIPS dynamically extensible processor, Microsoft research technical report MSR-TR-2007-155

  45. OpenRISC Debugging. (2011) http://www.opencores.org/openrisc,debugging

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Acknowledgments

This work was supported by a 2-Year Research Grant of Pusan National University.

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Authors and Affiliations

  1. Department of Electronics Engineering, Pusan National University, Busan, South Korea

    Hyeongbae Park, Jingzhe Xu & Jusung Park

  2. Department of Computer Engineering, Pusan National University, Busan, South Korea

    Jeong-Hoon Ji & Gyun Woo

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  1. Hyeongbae Park
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  2. Jingzhe Xu
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Correspondence to Jusung Park.

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Park, H., Xu, J., Ji, JH. et al. Design methodology for on-chip-based processor debugger. Des Autom Embed Syst 19, 35–57 (2015). https://doi.org/10.1007/s10617-014-9135-8

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