1. FTL algorithms for NAND-type flash memories

   • Se Jin Kwon
   • Arun Ranjitkar
   • Tae-Sun Chung

   OriginalPaper 09 March 2011 Pages: 191 - 224

2. Enhancing IP cores specifications using hierarchical composition and set theory

   • Cássio L. Rodrigues
   • Karina R. G. da Silva
   • Elmar Melcher

   OriginalPaper 08 April 2011 Pages: 225 - 245

3. FPGA automatic re-synchronisation for pipelined, floating point control systems applications

   • Beniamin Apopei
   • Tony J. Dodd

   OriginalPaper 09 June 2011 Pages: 247 - 288

4. HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors

   • Mostafa Kishani
   • Hamid R. Zarandi
   • Behnam Ghavami

   OriginalPaper 15 May 2011 Pages: 289 - 310

5. A retargetable framework for compiler/architecture co-development

   • Hanno Scharwaechter
   • David Kammler
   • Heinrich Meyr

   OriginalPaper 08 October 2011 Pages: 311 - 342