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FPGA automatic re-synchronisation for pipelined, floating point control systems applications

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Abstract

One of the main challenges in Systems designs is the ability to integrate real time high fidelity models on suitable and feasible hardware platforms. Because of its inherited parallelism, FPGA (Field Programmable Gate Arrays) technology achieves sample rates which are typically faster than real time. This can be seen as the last line of defence against the increasing requirements given by high fidelity models. But as most of the FPGA applications are specialised and the FPGA toolsets do not support basic control systems blocks, designs are constructed and optimised manually. This leads to significant effort required in finding feasible hardware FPGA implementations. Therefore, the work in this paper describes how to automatically optimise the most time consuming process found in generic FPGA implementations: the optimisation of the pipelining process. This is constructed on a rigorous mathematical model and achieved using drag and drop floating point HDL (Hardware Description Language) control systems blocks, under System Generator, in Simulink.

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References

  1. Guo Y, Mccain D, Zhang J (2003) Scalable FPGA architectures for LMMSE-based SIMO chip equalizer. In: SDPA downlink, IEEE asilomar conference on signals, systems, and computers, pp 2171–2175

    Google Scholar 

  2. Messmer P, Ranjbar V, Wade-Stein D, Schoessow P (2007) Advanced accelerator control and instrumentation modules based on FPGA. In: Particle accelerator conference, pp 506–508

    Google Scholar 

  3. Vacek G, Mullally D, Christensen K (2008) Trends in high-performance computing requirements for computer-aided drug design. Curr Comput-Aided Drug Des 4:2–12

    Article  Google Scholar 

  4. Monmasson E, Cirstea MN (2007) FPGA design methodology for industrial control systems—a review. IEEE Trans Ind Electron 54(4):1824–1897

    Article  Google Scholar 

  5. Tian X, Benkrid K (2009) American option pricing on reconfigurable hardware using least-squares Monte Carlo method. In: Proc int conf on field-programmable technology, pp 263–270

    Chapter  Google Scholar 

  6. Mills AR, Apopei B, Mangion AZ, Barron-Gonzales H, Gunetti P, Thompson HA, Garbett P (2010) Heterogeneous hardware technologies for accelerating complex aerospace system simulations. In: Aerospace conference, 2010 IEEE, 6–13 March 2010, pp 1–10. doi:10.1109/AERO.2010.5446789

    Chapter  Google Scholar 

  7. Ahlquist G, Rice M, Nelson B (1999) Error control coding in software radios: an FPGA approach. IEEE Personal Comms, August 1999

  8. Jamali MM, Tran BJ (2008) FPGA based sensory/actuation embedded system. In: Aerospace and electronics conference, NAECON 2008. IEEE national, New York, pp 246–249

    Chapter  Google Scholar 

  9. Simard S, Mailloux JG, Beguenane R (2009) Prototyping advanced control systems on FPGA. In: EURASIP J Embed Syst—FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms

    Google Scholar 

  10. Kelvin Ng (2008) Challenges in using system-level models for RTL verification. In: Proceedings of the 45th annual design automation conference, pp 812–815

    Google Scholar 

  11. Blair A, Brown T, Cromwell J, Kim S, Milne R (2007) Porting lessons learned from soldier radio waveform (SRW). In: Military commun. conf., MILCOM 2007. IEEE, New York, pp 1–6

    Chapter  Google Scholar 

  12. Baidas Z, Brown AD, Williams AC (2001) Floating-point behavioral synthesis. IEEE Trans Comput-Aided Des Integr Circuits Syst 20(7)

  13. Astarloa A, Lázaro J, Bidarte U, Jiménez J, Zuloaga A (2009) FPGA technology for multi-axis control systems. Mechatronics 19(2):258–268

    Article  Google Scholar 

  14. Rice M, Padilla M, Nelson B (2009) On FM demodulators in software defined radios using FPGAs. In: Military communications conference, MILCOM 2009. IEEE, New York, pp 1–7

    Google Scholar 

  15. Piqtek P, Grega W (2009) Speed analysis of a digital controller in time critical applications. J Autom Mob Robot Intell Syst 3(1):57–61

    Google Scholar 

  16. Wang JJ, Katz RB, Sun JS, Cronquist BE, McCollum JL, Speers TM, Plants WC (1999) SRAM based reprogrammable FPGA for space applications. IEEE Trans Nucl Sci 46(6):1728–1735

    Article  Google Scholar 

  17. Sridharan K, Priya TK (2005) The design of a hardware accelerator for real-time complete visibility graph construction and efficient FPGA implementation. IEEE Trans Ind Electron 52(4):1185–1187

    Article  Google Scholar 

  18. Li THS, Shih-Jie C, Yi-Xiang C (2003) Implementation of humanlike driving skills by autonomous fuzzy behavior control on an FPGA based car-like mobile robot. IEEE Trans Ind Electron 50(5):867–880

    Article  Google Scholar 

  19. Chang TN, Cheng B, Sriwilaijaroen P (2006) Motion control firmware for high-speed robotic systems. IEEE Trans Ind Electron 53(5):1713–1722

    Article  Google Scholar 

  20. Litayem N, Ghrissi M, Salem AKB, Saoud SB (2009) Designing and building embedded environment for robotic control application. In: 35th annual conference of IEEE industrial electronics, pp 2907–2912

    Chapter  Google Scholar 

  21. Geist A, Lucas R (2009) Major computer science challenges at exascale. Int J High Perform Comput Appl 23(4):427–436

    Article  Google Scholar 

  22. Xilinx (2009a) [Online]. Available at: http://www.xilinx.com/ise/optional_prod/system_generator.htm. Accessed 8 Nov 2010

  23. Kitchenham B, Linkman S, Law D (1997) DESMET: a methodology for evaluating software eng methods and tools. Comput Control Eng J 8:120–6

    Article  Google Scholar 

  24. Wain R, Bush I, Guest M, Deegan M, Kozin I, Kitchen C (2006) An overview of FPGAs and FPGA programming; initial experiences at Daresbury. Computational Science and Engineering Department, CCLRC Daresbury Laboratory, Daresbury, Warrington, Cheshire, November 2006

  25. Todman TJ, Constantinides GA, Wilton SJE, Mencer O, Luk W, Cheung PYK (2010) Reconfigurable computing architectures, tools and applications. In: 6th international symposium, ARC, Bangkok, Thailand, March 17–19, 2010

    Google Scholar 

  26. Altera. Home Page [Online] (Updated 2010). Available at: http://www.altera.com. Accessed 08 Nov 2010

  27. Xilinx. Home Page [Online] (Updated 2010). Available at: http://www.xilinx.com. Accessed 08 Nov 2010

  28. Mentor Graphics. Catapult C Synthesis [Online] (Updated 2010). Available at: http://www.mentor.com/products/esl/high_level_synthesis/catapult_synthesis. Accessed 08 Nov 2010

  29. Handle C Manual [Online] (Updated 2010). Available at: http://www.agilityds.com/literature/HandelC_Language_Reference_Manual.pdf. Accessed 08 Nov 2010

  30. Edwards SA (2004) The challenges of hardware synthesis from C-like languages. In: Proceedings of the international workshop of logic and synthesis, IWLS

    Google Scholar 

  31. System C level design [Online] (Updated 2010). Available at: http://system-synthesis.org/. Accessed 08 Nov 2010

  32. Impulse Accelerated Technologies [Online] (Updated 2010). Available at: http://www.impulseaccelerated.com. Accessed 08 Nov 2010

  33. Calipto SLEC RTL Verification [Online] (Updated 2010). Available at: http://www.calypto.com/slecrtl.php. Accessed 08 Nov 2010

  34. Calipto News Release [Online] (Updated 2010). Available at: http://www.calypto.com/news/NewsRelease_06_07_10.pdf. Accessed 08 Nov 2010

  35. Graphics Mentor, Synthesis Product C [Online] (Updated 2010). Available at: http://www.mentor.com/products/esl/news/catpultc_productextension. Accessed 08 Nov 2010

  36. Hitech Global. Xilinx ISE Foundation [Online] (Updated 2010). Available at: http://www.hitechglobal.com/designtools/xilinxise.htm. Accessed 08 Nov 2010

  37. Takach A, Bower B, Bollaert T (2005) C based hardware design for wireless applications. In: Design, Automation and Test in Europe

    Google Scholar 

  38. Mathworks. Simulink HDL coder. [Online] (Updated 2010). Available at: http://www.mathworks.com/access/helpdesk/help/toolbox/slhdlcoder. Accessed 8 Nov 2010

  39. Xilinx. Core generator user guide [Online] (Updated 2010). Available at: http://homepages.cae.wisc.edu/~ece554/website/Xilinx/Coregen_user_guide.pdf. Accessed 8 Nov 2010

  40. Altera. J Stephenson (Updated 2005). Design guidelines for optimal results in FPGAs [Online] Available at: http://www.altera.com/literature/cp/fpgas-optimal-results-396.pdf. Accessed 26 April 2010

  41. Hutton M (Updated 2006) Chapter 4 characterization of sequential circuits. PhD thesis [Online] Available at: http://www.eecg.toronto.edu/~mdhutton/papers/thesis4.pdf. Accessed 26 April 2010

  42. Lopes A, Constantinides G, Kerrigan EC (2008) A floating-point solver for band structured linear equations. In: Proc int conf field programmable technology, pp 353–356

    Chapter  Google Scholar 

  43. Govindu G, Zhuo L, Choi S, Prasanna V (2004) Analysis of high-performance floating-point arithmetic on FPGAs. In: Proceedings of the 18th international parallel and distributed processing symposium, IPDPS’04, pp 149–156

    Chapter  Google Scholar 

  44. Apopei B, Mills A, Dodd T, Thompson H (2009) Real time simulation in floating point precision using FPGA computing. In: Reconfigurable computing: architectures, tools and applications, ARC 2009, pp 349–354

    Chapter  Google Scholar 

  45. Goodwin GC, Graebe SF, Salgado ME control system design. Prentice Hall, Englewood Cliffs

  46. Liang D, Harrold MJ (1999) Equivalence analysis: a general technique to improve the efficiency of data-flow analyses in the presence of pointers. In: Proceedings of the 1999 ACM SIGPLAN-SIGSOFT workshop on program analysis for software tools and engineering, Toulouse, France, pp 39–46

    Chapter  Google Scholar 

  47. Murata T (1989) Petri nets: properties, analysis and applications. Proc IEEE 77(4)

  48. Sudacevschi V, Gutuleac L, Ababii V (2004) A hardware implementation of petri nets models. In: 7th international conference on development and application systems, Suceava, Romania, May 27–29, 2004

    Google Scholar 

  49. Pastor E, Roig O, Cortadella J, Badia RM (1994) Petri net analysis using boolean manipulation. In: Proc application and theory of petri nets. LNCS, vol 825, pp 416–435

    Google Scholar 

  50. Teifel J, Manohar R (2004) Static tokens: using dataflow to automate concurrent pipeline synthesis. In: 10th int’l symposium on advanced research in asynchronous circuits and systems, pp 17–27

    Chapter  Google Scholar 

  51. Barad M (1998) Timed Petri Nets as a verification tool. In: Proceedings of the 30th conference on winter simulation, Washington, DC, USA, pp 547–554

    Google Scholar 

  52. Huang S-T, Pamg T-M, Shyu J-M (1994) Timed boolean calculus and its applications in timing analysis. IEEE Trans Comput-Aided Des Integr Circuits Syst 13(3)

  53. Lam WKC, Brayton RK (1994) Timed boolean functions: a unified formalism for exact timing analysis. Kluwer Academic, Dordrecht

    MATH  Google Scholar 

  54. Nilsson H (2003) Functional automatic differentiation with Dirac impulses. Accepted for publication at ICFP 2003, Uppsala, Sweden

  55. Lee EA (1991) Consistency in dataflow graphs. IEEE Trans Parallel Distrib Syst 2(2)

  56. Bhattacharya B, Bhattacharyya SS (2001) Parameterized dataflow modeling for DSP systems. IEEE Trans Signal Process 49(10):2408–2421

    Article  MathSciNet  Google Scholar 

  57. Berthomieu B, Diaz M (1991) Modeling and verification of time dependent systems using time petri nets. IEEE Trans Softw Eng 17(3):259–273

    Article  MathSciNet  Google Scholar 

  58. Ziegler H, So B, Hall M, Diniz P (2002) Coarse-grain pipelining for multiple FPGA architectures. In: Proc of the IEEE symp on FPGA for custom computing machines, FCCM’02

    Google Scholar 

  59. Matlab 2006. Simulink Demo [Online] (Updated 2010). Available at: http://www.mathworks.co.uk/products/simulink/demos.html?file=/products/demos/shipping/simulink/sldemo_suspn.html. Accessed 13 Nov 2010

  60. Rodriguez BF (2006) Half car suspension model. In: UTPA–MECE 4333, Vehicle systems modeling and control

    Google Scholar 

  61. Matlab Simulink [Online] (Updated 2010). Available at: http://www.mathworks.com/access/helpdesk/help/toolbox/simulink/index.html?/access/helpdesk/help/toolbox/simulink/slref/bq3cxmi.html. Accessed 13 Nov 2010

  62. Synopsys. HAPS 52 [Online] (Updated 2007). Available at: http://www.synopsys.co.jp/literature/haps/datasheets/haps_summary-ds.pdf. Accessed 12 Nov 2010

  63. Leiserson CE, Saxe JB (1991) Retiming synchronous circuitry. Algorithmica, 5–35

  64. Xilinx XST manual [Online] (Updated 2010). Available at: http://www.xilinx.com/itp/xilinx5/pdf/docs/xst/xst.pdf. Accessed 13 Nov 2010

  65. Singh KJ, Wang AR, Brayton RK, Sangiovanni-Vincentelli A (1988) Timing optimisation of combinational logic. In: Proc IEEE conf computer-aided design, pp 282–285

    Google Scholar 

  66. Iqbal Z, Potkonjak M, Dey S, Parker A (1993) Critical path minimization using retiming and algebraic speed-up. In: Proceedings of the 30th international conference on design automation, June 14–18, 1993, Dallas, Texas, United States, pp 573–577

    Google Scholar 

  67. Malik A (2005) Design trade-off analysis of floating-point adder in FPGAs. MS thesis, Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, Canada

  68. Mathworks (Updated 2010). Jet Transport model [Online]. Available at: http://www.mathworks.com/help/toolbox/control/getstart/f1-1012205.html. Accessed 8 Nov 2010

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Authors and Affiliations

  1. Department of Automatic Control and Systems Engineering, The University of Sheffield, Mappin Street, Sheffield, S1 3JD, UK

    Beniamin Apopei & Tony J. Dodd

  2. 240 Marmion St., Cottesloe, Western Australia, 6011, Australia

    Beniamin Apopei

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  1. Beniamin Apopei
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  2. Tony J. Dodd
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Correspondence to Beniamin Apopei.

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Apopei, B., Dodd, T.J. FPGA automatic re-synchronisation for pipelined, floating point control systems applications. Des Autom Embed Syst 15, 247–288 (2011). https://doi.org/10.1007/s10617-011-9077-3

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