Abstract
In this paper, a high performance software framework based on multi-level hash table for instruction-set simulator (ISS) is presented. This framework not only enhances the extensibility in Develop-Time by filling out the file of instruction set definition, but also improves the efficiency in Run-Time by loading the instruction identification table and the parameter information table in Compile-Time. This software framework is evaluated by several experiments based on c6xsim [1]. It can be ported to any ISS that simulate the processors with any architecture conveniently, and provides 1-to-2x speedups.
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Hao, Z., Chu, P., Zhang, T., Wang, D., Hou, C. (2012). A High-Performance Framework for Instruction-Set Simulator. In: Qian, Z., Cao, L., Su, W., Wang, T., Yang, H. (eds) Recent Advances in Computer Science and Information Engineering. Lecture Notes in Electrical Engineering, vol 128. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-25792-6_2
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DOI: https://doi.org/10.1007/978-3-642-25792-6_2
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