Incremental Circuit Simulation for Large-Scale MOSFET Circuits with Interconnects Using Iterated Timing Analysis

Abstract

The circuit level incremental simulation is a good strategy to reduce the circuit simulation time, since most circuit designers use circuit simulators to simulate incrementally modified circuits repeatedly. This paper researches the large-scale incremental circuit simulation using the well-known ITA (Iterated Timing Analysis) algorithm. The target circuits are popular MOSFET circuits containing interconnects that are modeled by transmission lines. This paper has proposed an efficient algorithm for incremental simulation, the method to handle transmission lines, and other time-saving techniques. Experimental results justify that proposed methods undertake large-scale incremental circuit simulation for MOSFET and transmission lines very well.