Abstract
This work presents a Model Driven Engineering (MDE) approach for the automatic generation of a network of timed automata from the functional specification of an embedded application described using UML class and sequence diagrams. By means of transformations on the UML model of the embedded system, a MOF-based representation for the network of timed automata is automatically obtained, which can be used as input to formal verification tools, as the Uppaal model checker, in order to validate desired functional and temporal properties of the embedded system specification. Since the network of timed automata is automatically generated, the methodology can be very useful for the designer, making easier the debugging and formal validation of the system specification. The paper describes the defined transformations between models, which generate the network of timed automata as well as the textual input to the Uppaal model checker, and illustrates the use of the methodology with a case study to show the effectiveness of the approach.
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Keywords
- Sequence Diagram
- Model Drive Engineer
- Model Drive Architecture
- Model Check Tool
- Model Drive Architecture
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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do Nascimento, F.A.M., da Silva Oliveira, M.F., Wagner, F.R. (2009). Formal Verification for Embedded Systems Design Based on MDE. In: Rettberg, A., Zanella, M.C., Amann, M., Keckeisen, M., Rammig, F.J. (eds) Analysis, Architectures and Modelling of Embedded Systems. IESS 2009. IFIP Advances in Information and Communication Technology, vol 310. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04284-3_15
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DOI: https://doi.org/10.1007/978-3-642-04284-3_15
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