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Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework

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Handbook of Hardware/Software Codesign

Abstract

Since the mid-1990s, Model-Driven Design (MDD) methodologies (Selic, IEEE Softw 20(5):19–25, 2003) have aimed at raising the level of abstraction through an extensive use of generic models in all the phases of the development of embedded systems. MDD describes the system under development in terms of abstract characterization, attempting to be generic not only in the choice of implementation platforms but even in the choice of execution and interaction semantics. Thus, MDD has emerged as the most suitable solution to develop complex systems and has been supported by academic (Ferrari et al., From conception to implementation: a model based design approach. In: Proceedings of IFAC symposium on advances in automotive control, 2004) and industrial tools (3S Software CoDeSys, 2012. http://www.3s-software.com; Atego ARTiSAN, 2012. http://www.atego.com/products/artisan-studio; Gentleware Poseidon for UML embedded edition, 2012. http://www.gentleware.com/uml-software-embedded-edition.html; IAR Systems IAR visualSTATE, 2012. http://www.iar.com/Products/IAR-visualSTATE/; rhapsodyIBM Rational Rhapsody, 2012. http://www.ibm.com/software/awdtools/rhapsody; entarchSparx Systems Enterprise architet, 2012. http://www.sparxsystems.com.au; Aerospace Valley TOPCASED project, 2012. http://www.topcased.org). The gain offered by the adoption of an MDD approach is the capability of generating the source code implementing the target design in a systematic way, i.e., it avoids the need of manual writing. However, even if MDD simplifies the design implementation, it does not prevent the designers from wrongly defining the design behavior. Therefore, MDD gives full benefits if it also integrates functional verification . In this context, Assertion-Based Verification (ABV) has emerged as one of the most powerful solutions for capturing a designer’s intent and checking their compliance with the design implementation. In ABV, specifications are expressed by means of formal properties. These overcome the ambiguity of natural languages and are verified by means of either static (e.g., model checking) or, more frequently, dynamic (e.g., simulation) techniques. Therefore ABV provides a proof of correctness for the outcome of the MDD flow. Consequently, the MDD and ABV approaches have been combined to create efficient and effective design and verification frameworks that accompany designers and verification engineers throughout the system-level design flow of complex embedded systems, both for the Hardware (HW) and the Software (SW) parts (STM Products radCHECK, 2012. http://www.verificationsuite.com; Seger, Integrating design and verification – from simple idea to practical system. In: Proceedings of ACM/IEEE MEMOCODE, pp 161–162, 2006). It is, indeed, worth noting that to achieve a high degree of confidence, such frameworks require to be supported by functional qualification methodologies, which evaluate the quality of both the properties (Di Guglielmo et al. The role of mutation analysis for property qualification. In: 7th IEEE/ACM international conference on formal methods and models for co-design, MEMOCODE’09, pp 28–35, 2009. DOI 10.1109/MEMCOD.2009.5185375) and the testbenches which are adopted during the overall flow (Bombieri et al. Functional qualification of TLM verification. In: Design, automation test in Europe conference exhibition, DATE’09, pp 190–195, 2009. DOI 10.1109/DATE.2009.5090656). In this context, the goal of the chapter consists of providing, first, a general introduction to MDD and ABV concepts and related formalisms and then a more detailed view on the main challenges concerning the realization of an effective semiformal ABV environment through functional qualification.

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Abbreviations

ABV:

Assertion-Based Verification

CTL:

Computation Tree Logic

DUV:

Design Under Verification

EFSM:

Extended Finite-State Machine

ES:

Embedded System

ESL:

Electronic System Level

FSM:

Finite-State Machine

HDL:

Hardware Description Language

HW:

Hardware

I/O:

Input/Output

LLVM:

Low-Level Virtual Machine

LTL:

Linear Time Logic

MARTE:

Modeling and Analysis of Real-Time Embedded Systems

MDA:

Model-Driven Architecture

MDD:

Model-Driven Design

MLBJ:

Multi-Level Back Jumping

MMIO:

Memory-Mapped I/O

MoC:

Model of Computation

OMG:

Object Management Group

OSCI:

Open SystemC Initiative

OVL:

Open Verification Library

PIM:

Platform Independent Model

PSL:

Property Specification Language

PSM:

Platform Specific Model

RTL:

Register Transfer Level

SERE:

Sequential Extended Regular Expression

SoC:

System-on-Chip

SVA:

System Verilog Assertions

SW:

Software

TLM:

Transaction-Level Model

UML:

Unified Modeling Language

VHDL:

VHSIC Hardware Description Language

VHSIC:

Very High Speed Integrated Circuit

References

  1. 3S Software (2012) CoDeSys. http://www.3s-software.com

  2. Abarbanel Y, Beer I, Gluhovsky L, Keidar S, Wolfsthal Y (2000) FoCs: automatic generation of simulation checkers from formal specifications. In: Proceedings of international conference on computer aided verification (CAV), pp 538–542

    Google Scholar 

  3. Aerospace Valley (2012) TOPCASED project. http://www.topcased.org

  4. Alagar V, Periyasamy K (2011) Extended finite state machine. In: Specification of software systems, texts in computer science. Springer, London, pp 105–128. DOI 10.1007/978-0-85729-277-3_7

    Chapter  Google Scholar 

  5. Alexander RT, Bieman JM, Ghosh S, Bixia J (2002) Mutation of Java objects. In: Proceedings of IEEE ISSRE, pp 341–351

    Google Scholar 

  6. Alur R, Dill DL (1994) A theory of timed automata. Theoret Comput Sci 126(2):183–235

    Article  MathSciNet  MATH  Google Scholar 

  7. Armoni R, Fix L, Flaisher A, Grumberg O, Piterman N, Tiemeyer A, Vardi M (2003) Enhanced vacuity detection in linear temporal logic (CAV). In: International conference on computer aided verification, vol 2725. Springer, Berlin/Heidelberg, pp 368–380

    Chapter  Google Scholar 

  8. Atego (2012) ARTiSAN. http://www.atego.com/products/artisan-studio

  9. Batth SS, Vieira ER, Cavalli A, Umit Uyar M (2007) Specification of timed EFSM fault models in SDL. In: Proceedings of FORTE, pp 50–65

    MATH  Google Scholar 

  10. Beer I, Ben-David S, Eisner U, Rodeh Y (1997) Efficient detection of vacuity in ACTL formulas. In: International conference on computer aided verification (CAV), vol 1254, pp 279–290

    Google Scholar 

  11. Beer I, Ben-David S, Eisner C, Rodeh Y (2001) Efficient detection of vacuity in temporal model checking. Form Methods Syst Des 18(2):141–163

    Article  MATH  Google Scholar 

  12. Belli F, Budnik CJ, Wong WE (2006) Basic operations for generating behavioral mutants. In: Proceedings of IEEE ISSRE, pp 10–18

    Google Scholar 

  13. Black P, Okun V, Yesha Y (2000) Mutation operators for specifications. In: Proceedings of IEEE ASE, pp 81–88

    Google Scholar 

  14. Bombieri N, Fummi F, Guarnieri V, Pravadelli G (2014) Testbench qualification of systemc TLM protocols through mutation analysis. IEEE Trans Comput 63(5):1248–1261

    Article  MathSciNet  MATH  Google Scholar 

  15. Bombieri N, Fummi F, Pravadelli G, Hampton M, Letombe F (2009) Functional qualification of TLM verification. In: Design, automation test in Europe conference exhibition, DATE’09, pp 190–195. DOI 10.1109/DATE.2009.5090656

    Google Scholar 

  16. Borrione D, Liu M, Morin-Allory K, Ostier P, Fesquet L (2005) On-line assertion-based verification with proven correct monitors. In: Proceedings of international conference on information and communications technology (ICICT), pp 125–143

    Google Scholar 

  17. Boulé M, Zilic Z (2008) Automata-based assertion-checker synthesis of PSL properties. ACM Trans Des Autom Electron Syst 13:1–21. http://doi.acm.org/10.1145/1297666.1297670

    Article  Google Scholar 

  18. Boutekkouk F, Benmohammed M, Bilavarn S, Auguin M et al (2009) UML 2.0 profiles for embedded systems and systems on a chip (SoCs). J Object Technol 8(1):135–157. DOI 10.5381/jot.2009.8.1.a1

    Article  Google Scholar 

  19. Bradbury JS, Cordy JR, Dingel J (2006) ExMan: a generic and customizable framework for experimental mutation analysis. In: Proceedings of IEEE ISSRE, pp 4–9

    Google Scholar 

  20. Bradbury JS, Cordy JR, Dingel J (2006) Mutation operators for concurrent Java (J2SE 5.0). In: Proceedings of IEEE ISSRE, pp 11–11

    Google Scholar 

  21. Brait S, Fummi F, Pravadelli G (2005) On the use of a high-level fault model to analyze logical consequence of properties. In: Proceedings of ACM/IEEE international conference on formal methods and models for co-design, MEMOCODE, pp 221–230

    Google Scholar 

  22. Cadar C, Dunbar D, Engler D (2008) KLEE: unassisted and automatic generation of high-coverage tests for complex systems programs. In: Proceedings of USENIX symposium on operating systems design and implementation (OSDI)

    Google Scholar 

  23. Cadar C, Ganesh V, Pawlowski PM, Dill DL, Engler DR (2006) EXE: a system for automatically generating inputs of death using symbolic execution. In: ACM conference on computer and communications security, pp 322–335

    Google Scholar 

  24. Cadence (2012) Assertion-based verification. http://www.cadence.com/products/fv/pages/abv_flow.aspx

  25. Cheng KT, Jou JY (1990) A single-state-transition fault model for sequential machines. In: IEEE ICCAD’90, pp 226–229

    Google Scholar 

  26. Cheung P, Forin A (2007) A C-language binding for PSL. In: Proceedings of international conference on embedded software and systems (ICESS). Springer, pp 584–591

    Google Scholar 

  27. Chockler H, Kupferman O, Kurshan R, Vardi M (2001) A practical approach to coverage in model checking. In: Proceedings computer aided and verification, pp 66–78

    MATH  Google Scholar 

  28. Chockler H, Kupferman O, Vardi M (2006) Coverage metrics for formal verification. Int J Softw Tools Technol Transfer (STTT) 8:373–386

    Article  MATH  Google Scholar 

  29. Chockler H, Kupferman O, Vardi M (2006) Coverage metrics for temporal logic model checking. Formal Methods Syst Des 28:189–212

    Article  MATH  Google Scholar 

  30. Chockler H, Strichman O (2007) Easier and more informative vacuity checks. In: Proceedings ACM/IEEE international conference on formal methods and models for codesign, pp 189–198

    Google Scholar 

  31. Choi BJ, DeMillo RA, Krauser EW, Martin RJ, Mathur AP, Pan AJOH, Spafford EH (1989) The Mothra tool set (software testing). In: Proceedings of IEEE HICSS, vol 2, pp 275–284

    Google Scholar 

  32. Chow T (1978) Testing software design modeled by finite state machines. IEEE Trans Softw Eng 4(3):178–187

    Article  MATH  Google Scholar 

  33. Dahan A, Geist D, Gluhovsky L, Pidan D, Shapir G, Wolfsthal Y, Benalycherif L, Kamidem R, Lahbib Y (2005) Combining system level modeling with assertion-based verification. In: Proceedings of international symposium on quality of electronic design (ISQED), pp 310–315

    Google Scholar 

  34. Das S, Mohanty R, Dasgupta P, Chakrabarti P (2006) Synthesis of system verilog assertions. In: Proceedings of design, automation & test in Europe conference & exhibition (DATE), vol 2, pp 1–6

    Google Scholar 

  35. De Simone R, André C (2006) Towards a “synchronous reactive” UML profile? Int J Softw Tools Technol Transfer 8(2):146–155

    Article  Google Scholar 

  36. Delamaro ME, Maldonado JC (1996) Proteum – a tool for the assessment of test adequacy for C programs. In: PCS’96, pp 79–95

    Google Scholar 

  37. DeMillo RA, Lipton RJ, Sayward FG (1978) Hints on test data selection: help for the practicing programmer. IEEE Comput 11(4):34–41

    Article  Google Scholar 

  38. Di Guglielmo G, Di Guglielmo L, Foltinek A, Fujita M, Fummi F, Marconcini C, Pravadelli G (2013) On the integration of model-driven design and dynamic assertion-based verification for embedded software. J Syst Softw 86(8):2013–2033. DOI 10.1016/j.jss.2012.08.061

    Article  Google Scholar 

  39. Di Guglielmo L, Fummi F, Pravadelli G (2009) The role of mutation analysis for property qualification. In: IEEE/ACM international conference on formal methods and models for co-design, MEMOCODE, pp 28–35

    Google Scholar 

  40. Di Guglielmo G, Fummi F, Pravadelli G, Soffia S, Roveri M (2010) Semi-formal functional verification by EFSM traversing via NuSMV. In: Proceedings of IEEE international high level design validation and test workshop (HLDVT), pp 58–65

    Google Scholar 

  41. Di Guglielmo L, Fummi F, Orlandi N, Pravadelli G (2010) DDPSL: an easy way of defining properties. In: 2010 IEEE international conference on computer design (ICCD), pp 468–473

    Google Scholar 

  42. Di Guglielmo L, Fummi F, Pravadelli G (2010) Vacuity analysis for property qualification by mutation of checkers. In: Design, automation test in Europe conference exhibition (DATE), pp 478–483

    Google Scholar 

  43. Di Guglielmo L, Fummi F, Pravadelli G, Stefanni F, Vinco S (2012) A formal support for homogeneous simulation of heterogeneous embedded systems. In: IEEE international symposium on industrial embedded systems (SIES), pp 211–219

    Google Scholar 

  44. Di Guglielmo L, Fummi F, Pravadelli G, Stefanni F, Vinco S (2013) UNIVERCM: the universal versatile computational model for heterogeneous system integration. IEEE Trans Comput 62(2):225–241

    Article  MathSciNet  MATH  Google Scholar 

  45. Ebeid E, Fummi F, Quaglia D (2015) HDL code generation from UML/MARTE sequence diagrams for verification and synthesis. Des Autom Embed Syst 19(3):277–299. DOI 10.1007/s10617-014-9158-1

    Article  Google Scholar 

  46. Ebeid E, Fummi F, Quaglia D (2015) Model-driven design of network aspects of distributed embedded systems. IEEE Trans Comput Aided Des Integr Circuits Syst 34(4):603–614

    Article  Google Scholar 

  47. Ebert C, Jones C (2009) Embedded software: facts, figures, and future. Computer 42(4):42–52

    Article  Google Scholar 

  48. Fedeli A, Fummi F, Pravadelli G (2007) Properties incompleteness evaluation by functional verification. IEEE Trans Comput 56(4):528–544

    Article  MathSciNet  Google Scholar 

  49. Ferrari A, Gaviani G, Gentile G, Stara G, Romagnoli G, Thomsen T (2004) From conception to implementation: a model based design approach. In: Proceedings of IFAC symposium on advances in automotive control

    Google Scholar 

  50. Ferro L, Pierre L (2010) ISIS: runtime verification of TLM platforms. Adv Des Methods Model Lang Embed Syst SoCs 63:213–226

    Google Scholar 

  51. Foster H, Krolnik A, Lacey D (2004) Assertion-based design. Springer, New York

    Google Scholar 

  52. Foster H, Larsen K, Turpin M (2006) Introducing the new accellera open verification library standard. In: Proceedings of design and verification conference (DVCON)

    Google Scholar 

  53. Gentleware (2012) Poseidon for UML embedded edition. http://www.gentleware.com/uml-software-embedded-edition.html

  54. Godefroid P, Klarlund N, Sen K (2005) DART: directed automated random testing. In: Proceedings of ACM SIGPLAN conference on programming language, design, and implementation (PLDI), pp 213–223

    Google Scholar 

  55. Graaf B, Lormans M, Toetenel H (2003) Embedded software engineering: the state of the practice. IEEE Softw 20(6):61–69

    Article  Google Scholar 

  56. Di Guglielmo L, Fummi F, Pravadelli G, Stefanni F, Vinco S (2011) UNIVERCM: The UNIversal VERsatile computational model for heterogeneous embedded system design. In: Proceedings of IEEE HLDVT, pp 33–40

    MATH  Google Scholar 

  57. HAL – Inria (2012) Gaspard2 UML profile documentation. http://hal.inria.fr/inria-00171137/en

  58. Henzinger T (1996) The theory of hybrid automata. In: Logic in computer science (LICS). IEEE Computer Society, New Brunswick, pp 278–292

    Google Scholar 

  59. Hiller M (2000) Executable assertions for detecting data errors in embedded control systems. In: Proceedings of IEEE international conference on dependable systems and networks (DSN), pp 24–33

    Google Scholar 

  60. Hoskote Y, Kam T, Ho P, Zhao X (1999) Coverage estimation for symbolic model checking. In: Proceedings ACM/IEEE design automation conference, pp 300–305

    Google Scholar 

  61. Hyunsook D, Rothermel G (2006) On the use of mutation faults in empirical assessments of test case prioritization techniques. IEEE Trans Softw Eng 32(9):733–752

    Article  Google Scholar 

  62. IAR Systems (2012) IAR visualSTATE. http://www.iar.com/Products/IAR-visualSTATE/

  63. IBM (2012) Rational Rhapsody. http://www.ibm.com/software/awdtools/rhapsody

  64. IEEE Computer Society (2010) IEEE Standard for Property Specification Language (PSL) (IEEE Std 1850-2010)

    Google Scholar 

  65. Jayakumar N, Purandare M, Somenzi F (2003) Dos and don’ts of CTL state coverage estimation. In: Proceedings of design automation conference (DAC)

    Google Scholar 

  66. Katz S, Grumberg O (1999) Have I written enough properties? – a method of comparison between specification and implementation. In: Proceedings ACM advanced research working conference on correct hardware design and verification methods. Springer, pp 280–297

    MATH  Google Scholar 

  67. Kim M, Kim Y, Kim H (2011) A comparative study of software model checkers as unit testing tools: an industrial case study. IEEE Trans Softw Eng 37(2):146–160

    Article  Google Scholar 

  68. King JC (1976) Symbolic execution and program testing. Commun ACM 19(7):385–394

    Article  MathSciNet  MATH  Google Scholar 

  69. Kupferman O, Vardi MY (1999) Vacuity detection in temporal model checking. In: Conference on correct hardware design and verification methods, pp 82–96

    MATH  Google Scholar 

  70. Kupferman O, Vardi M (2003) Vacuity detection in temporal model checking. Int J Softw Tools Technol Transfer 4(2):224–233

    Article  MATH  Google Scholar 

  71. Kupferman O, Li W, Seshia S (2008) A theory of mutations with applications to vacuity, coverage, and fault tolerance. In: Proceedings IEEE international conference on formal methods in computer-aided design

    Book  Google Scholar 

  72. Lattner C, Adve V (2005) The LLVM compiler framework and infrastructure tutorial. In: Proceedings of international workshop on languages and compilers for high performance computing (LCPC). Springer, pp 15–16

    Google Scholar 

  73. Lee T, Hsiung P (2004) Mutation coverage estimation for model checking. In: Proceedings international symposium on automated technology for verification and analysis, pp 354–368

    MATH  Google Scholar 

  74. Lettnin D, Nalla P, Ruf J, Kropf T, Rosenstiel W, Kirsten T, Schonknecht V, Reitemeyer S (2008) Verification of temporal properties in automotive embedded software. In: Proceedings of design, automation & test in Europe conference & exhibition (DATE). ACM, pp 164–169

    Google Scholar 

  75. Lyu MR, Zubin H, Sze SKS, Xia C (2003) An empirical study on testing and fault tolerance for software reliability engineering. In: Proceedings of IEEE ISSRE, pp 119–130

    Google Scholar 

  76. Ma YS, Offutt J, Kwon YR (2005) Mujava: an automated class mutation system. Softw Test Verif Reliab 15(2):97–133

    Article  Google Scholar 

  77. Majumdar R, Sen K (2007) Hybrid concolic testing. In: Proceedings of IEEE international conference on software engineering (ICSE), pp 416–426

    Google Scholar 

  78. Mathur AP (1991) Performance, effectiveness, and reliability issues in software testing. In: COMPSAC’91, pp 604–605

    Google Scholar 

  79. McMinn P (2004) Search-based software test data generation: a survey. Softw Test Verif Reliab 14(2):105–156

    Article  Google Scholar 

  80. Mentor Graphics (2012) Assertion-based verification. http://www.mentor.com/products/fv/methodologies/abv

  81. Mischkalla F, He D, Mueller W (2010) A UML profile for SysML-based comodeling for embedded systems simulation and synthesis. In: Proceedings of workshop on model based engineering for embedded system design (MBED)

    Google Scholar 

  82. Mishra P, Dutt N (2002) Automatic functional test program generation for pipelined processors using model checking. In: Proceedings IEEE high-level design validation and test, pp 99–103

    Google Scholar 

  83. Object Management Group, Inc. (2012) MARTE resource page. http://www.omgmarte.org/

  84. Object Management Group, Inc. (2012) OMG specifications. http://www.omg.org

  85. Object Management Group, Inc. (2012) UML resource page. http://www.uml.org

  86. Offutt AJ, Untch RH (2001) Mutation 2000: uniting the orthogonal. In: Wong WE (ed) Mutation testing for the new century. Kluwer Academic Publishers, Boston, pp 34–44

    Chapter  Google Scholar 

  87. Offutt AJ, Rothermel G, Zapf C (1993) An experimental evaluation of selective mutation. In: ICSE’93, pp 100–107

    Google Scholar 

  88. Olsson T, Runeson P (2001) System level mutation analysis applied to a state-based language. In: Proceedings of IEEE ECBS, pp 222–228

    Google Scholar 

  89. Pinto Ferraz Fabbri SC, Delamaro ME, Maldonado JC, Masiero PC (1994) Mutation analysis testing for finite state machines. In: IEEE ISSRE’94, pp 220–229

    Google Scholar 

  90. Riccobene E, Scandurra P, Bocchio S, Rosti A, Lavazza L, Mantellini L (2009) SystemC/C-based model-driven design for embedded systems. ACM Trans Embed Comput Syst 8(4):1–37

    Article  Google Scholar 

  91. Seger C (2006) Integrating design and verification – from simple idea to practical system. In: Proceedings of ACM/IEEE MEMOCODE, pp 161–162

    Google Scholar 

  92. Selic B (2003) The pragmatics of model-driven development. IEEE Softw 20(5):19–25

    Article  Google Scholar 

  93. Sen K, Agha G (2006) CUTE and jCUTE: Concolic unit testing and explicit path model-checking tools. In: Proceedings of international conference on computer aided verification (CAV). Springer, Berlin/New York, pp 419–423

    Chapter  Google Scholar 

  94. Society IC (2009) IEEE standard for system verilog-unified hardware design, specification, and verification language (IEEE Std 1800-2009)

    Google Scholar 

  95. Sparx Systems (2012) Enterprise architet. http://www.sparxsystems.com.au

  96. STM Products (2012) radCHECK. http://www.verificationsuite.com

  97. SysML Partners (2012) SysML resource page. http://www.sysml.org

  98. The MathWorks, Inc. (2012) Simulink. http://www.mathworks.com/products/simulink/

  99. Tillmann N, De Halleux J (2008) Pex: white box test generation for. NET. In: Proceedings of ACM international conference on tests and proofs (TAP), pp 134–153

    Google Scholar 

  100. Winterholer M (2006) Transaction-based hardware software co-verification. In: Proceedings of forum on specification & design languages (FDL)

    Google Scholar 

  101. Xie F, Liu H (2007) Unified property specification for hardware/software co-verification. In: Proceedings of international computer software and applications conference (COMSAC), pp 483–490

    Google Scholar 

  102. Xu X, Kimura S, Horikawa K, Tsuchiya T (2005) Transition traversal coverage estimation for symbolic model checking. In: Proceedings ACM/IEEE international conference on formal methods and models for co-design, pp 259–260

    Google Scholar 

  103. Xu X, Kimura S, Horikawa K, Tsuchiya T (2006) Transition-based coverage estimation for symbolic model checking. In: Proceedings ACM/IEEE Asia and South Pacific conference on design automation, pp 1–6

    Google Scholar 

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Authors and Affiliations

  1. Università di Verona, Verona, Italy

    Graziano Pravadelli, Davide Quaglia & Franco Fummi

  2. Politecnico di Torino, Turin, Italy

    Sara Vinco

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  1. Graziano Pravadelli
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  2. Davide Quaglia
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  4. Franco Fummi
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Correspondence to Graziano Pravadelli .

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  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Pravadelli, G., Quaglia, D., Vinco, S., Fummi, F. (2017). Semiformal Assertion-Based Verification of Hardware/Software Systems in a Model-Driven Design Framework. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_23

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