Abstract
SafeCap is a modern toolkit for modelling, simulation and formal verification of railway networks. This paper discusses the use of SafeCap for formal analysis and fully-automated scalable safety verification of solid state interlocking (SSI) programs – a technology at the heart of many railway signalling solutions. The focus of the work is on making it easy for signalling engineers to use the developed technology and thus to help with its smooth industrial deployment. In this paper we explain the formal foundations of the proposed method, its tool support, and their application to real life railway verification problems.
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Notes
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With the unfortunate exception of arithmetics that is handled as a black-box rewrite.
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For more details, see http://alt-ergo.lri.fr/ and https://cs.nyu.edu/acsys/cvc3/.
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Iliasov, A., Taylor, D., Laibinis, L., Romanovsky, A. (2018). Formal Verification of Signalling Programs with SafeCap. In: Gallina, B., Skavhaug, A., Bitsch, F. (eds) Computer Safety, Reliability, and Security. SAFECOMP 2018. Lecture Notes in Computer Science(), vol 11093. Springer, Cham. https://doi.org/10.1007/978-3-319-99130-6_7
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