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Statistical Design of Integrated Circuits

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Low-Power Variation-Tolerant Design in Nanometer Silicon

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Abstract

The presence of process variations makes it imperative to depart from the traditional corner-based methodology and migrate to statistical design techniques. In this chapter, based on a set of variational models that capture correlated as well as uncorrelated variations, we present techniques for presilicon statistical timing and power analysis to determine the performance spread over a population of manufactured parts. In order to improve this spread, we discuss presilicon statistical optimization techniques that incorporate appropriate margins to enable improved manufacturing yield. At the post-silicon stage, we then present how a set of compact sensors may be used to predict the delay of a manufactured part, with known confidence, through a small set of measurements on the sensors: such data can then be used to drive adaptive post-silicon tuning approaches that are individualized to each manufactured part.

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Notes

  1. 1.

    Equivalently, its integral, the cumulative density function (CDF), may be provided.

  2. 2.

    The nominal value of the delay of the circuit is the delay value when no parameter variations are present. This can be computed exactly by a conventional static timing analysis with all parameters at their nominal values. However, because of the approximation of the max operation in the statistical timer, the mean value computed from the topological traversal is more compatible with the rest of the canonical form.

  3. 3.

    To consider the effect of varying N d on \(I_{\mathrm{sub}}\), equation (4.21) can be adapted by adding an additional term for \(\Delta N_\mathrm{d}\) in the exponent. As in the case of \(T_{\mathrm{ox}}\), the variation of N d does not show spatial correlation, and thus N d can be handled using a similar method as used for \(T_{\mathrm{ox}}\) in the framework.

  4. 4.

    An approximation of the sum of correlated lognormal random variables by Monte Carlo simulations is computationally difficult for large-sized problems. As an alternative, three analytical approaches have been overviewed and compared in [40]: Wilkinson’s approach, Schwartz and Yeh’s approach, and the cumulant-matching approach. Through numerical comparisons, [40] concluded that Wilkinson’s method is the best in terms of computational simplicity and accuracy.

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Acknowledgments

The author would like to thank Hongliang Chang, Qunzeng Liu, and Jaskirat Singh, whose work has contributed significantly to the content of this chapter.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA

    Sachin S. Sapatnekar

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Correspondence to Sachin S. Sapatnekar .

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  1. Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Euclid Avenue 10900, Cleveland, 44106-7071, Ohio, USA

    Swarup Bhunia

  2. School of Electrical &, Computer Engineering, Georgia Institute of Technology, Ferst Drive 266, Atlanta, 30332-0250, Georgia, USA

    Saibal Mukhopadhyay

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Sapatnekar, S.S. (2011). Statistical Design of Integrated Circuits. In: Bhunia, S., Mukhopadhyay, S. (eds) Low-Power Variation-Tolerant Design in Nanometer Silicon. Springer, Boston, MA. https://doi.org/10.1007/978-1-4419-7418-1_4

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  • DOI: https://doi.org/10.1007/978-1-4419-7418-1_4

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