Editors:
- Presents important challenges in nanometer scale integrated circuit design
- Presents a holistic view of Low-Power Variation-Tolerant Design
- Covers modeling, analysis and design methodology for low power and variation-tolerant logic circuits, memory and systems
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Table of contents (12 chapters)
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Front Matter
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Physics of Power Dissipations and Parameter Variations
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Front Matter
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Circuit-Level Design Solutions
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Front Matter
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System-Level Design Solutions
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Front Matter
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Low-Power and Robust Reconfigurable Computing
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Front Matter
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Back Matter
About this book
Keywords
Editors and Affiliations
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Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Cleveland, USA
Swarup Bhunia
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School of Electrical &, Computer Engineering, Georgia Institute of Technology, Atlanta, USA
Saibal Mukhopadhyay
Bibliographic Information
Book Title: Low-Power Variation-Tolerant Design in Nanometer Silicon
Editors: Swarup Bhunia, Saibal Mukhopadhyay
DOI: https://doi.org/10.1007/978-1-4419-7418-1
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media, LLC 2011
Hardcover ISBN: 978-1-4419-7417-4Published: 24 November 2010
Softcover ISBN: 978-1-4899-8157-8Published: 10 October 2014
eBook ISBN: 978-1-4419-7418-1Published: 10 November 2010
Edition Number: 1
Number of Pages: XV, 440
Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design