Abstract
Today’s complex embedded systems integrate multiple hardware and software components, many of them provided as IP from different vendors. Performance analysis is crucial for such heterogeneous systems. There already exists a variety of formal timing analysis techniques for small sub-problems, e. g. task performance, scheduling strategies, etc.. In this paper, we analyze these individual approaches in the context of performance analysis of heterogeneous platforms at different levels of abstraction, and present a three-level bottom-up analysis procedure.
The updated original online version for this book can be found at DOI: 10.1007/978-0-387-35599-3_29
Chapter PDF
Similar content being viewed by others
References
Rajeev Alur and David L. Dill. A theory of timed automata. Theoretical Computer Science, 126 (2): 183–235, 1994.
N. C. Audsley, A. Burns, M. F. Richardson, K. Tindell, and A. J. Wettings. Applying new scheduling theory to static priority preemptive scheduling. Journal of Real-Time Systems, 8 (5): 284–292, 1993.
Cadence. Cierto VCC Environment. http://www.cadence.com/products/vcc.html.
CoWare. CoWare N2C. http://www.coware.com/cowareN2C.html.
R. Ernst, D. Ziegenbein, K. Richter, L. Thiele, and J. Teich. Hardware/software codesign of embedded systems - The SPI Workbench. In Proceedings IEEE Workshop on VLSI, Orlando, USA, June 1999.
Christian Ferdinand and Reinhard Wilhelm. On predicting data cache behavior for real-time systems. In Proceedings of International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), pages 16–30, 1998.
K. Gresser. An event model for deadline verification of hard real-time systems. In Proceedings 5th Euromicro Workshop on Real-Time Systems, pages 118–123, Oulu, Finland, 1993.
C. Healy, R. Arnold, F Mueller, D. Whalley, and M. Hannon. Bounding pipeline and instruction cache performance. IEEE Transactions on Computers, pages 53–70, January 1999.
A. Hergenhan and W. Rosenstiel. Static timing analysis of embedded software on advanced processor architectures. In Proceedings of Design, Automation and Test in Europe (DATE ‘00), pages 552–559, Paris, March 2000.
H. Kopetz and G. Gruensteidl. TTP–a time-triggered protocol for fault-tolerant computing. In Proceedings 23rd International Symposium on Fault-Tolerant Computing, pages 524–532, 1993.
C.-G. Lee, J. Hahn, Y-M. Seo, S. L. Min, R. Ha, S. Hong, C. Y. Park, M. Lee, and C. S. Kim. Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In IEEE Transactions on Computers, pages 700–713, 1998.
J. Lehoczky. Fixed priority scheduling of periodic task sets with arbitrary deadlines. In Proceedings Real-Time Systems Symposiom, pages 201–209, 1990.
Yau-Tsun Steven Li and Sharad Malik. Performance Analysis of Real-Time Embedded Software. Kluwer Academic Publishers, 1999.
C. L. Liu and J. W. Layland. Scheduling algorithms for multiprogramming in a hard-realtime environment. Journal of the ACM, 20 (1): 46–61, 1973.
T. Lundquist and P. Stenström. Integrating path and timing analysis using instruction level simulation techniques. In Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems, Montreal, Canada, June 1998.
Mentor Graphics. Seamless Co-Verification Environment. http://www.mentorg.com/seamless.
P. Pop, P. Eles, and Z. Peng. Bus access optimization for distributed embedded systems based on schedulability analysis. In Proc. Design, Automation and Test in Europe (DATE 2000), Paris, France, 2000.
K. Richter and R. Ernst. Event model interfaces for heterogeneous system analysis. In Proc. of Design, Automation and Test in Europe Conference (DATE’02), Paris, France, March 2002.
K. Richter, D. Ziegenbein, R. Ernst, L. Thiele, and J. Teich. Model composition for scheduling analysis in platform design. In submitted to Proceeding 39th Design Automation Conference, New Orleans, USA, June 2002.
L. Sha, R. Rajkumar, and S. S. Sathaye. Generalized rate-monotonic scheduling theory: A framework for developing real-time systems. Proceedings of the IEEE, 82 (1): 68–82, January 1994.
B. Sprunt, L. Sha, and J. Lehoczky. Aperiodic task scheduling for hard real-time systems. Journal of Real-Time Systems, 1 (1): 27–60, 1989.
Synopsys. CoCentric System Studio. http://www.synopsys.com/products/cocentric_studio.
L. Thiele, s. Chakraborty, M. Gries, A. Maxiaguine, and J. Greutert. Embedded software in network processors - models and algorithms. In Proc. 1st Workshop on Embedded Software (EMSOFT), Lake Tahoe (CA), USA, October 2001.
K. W. Tindell. An extendible approach for analysing fixed priority hard real-time systems. Journal of Real-lime Systems, 6 (2): 133–152, Mar 1994.
F. Wolf and R. Ernst. Execution Cost Interval Refinement in Static Software Analysis. The EUROMICRO Journal, Special Issue on Modern Methods and Tools in Digital System Design, 47 (3–4): 339–356, April 2001.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 IFIP International Federation for Information Processing
About this chapter
Cite this chapter
Richter, K., Ziegenbein, D., Jersak, M., Ernst, R. (2002). Bottom-Up Performance Analysis of HW/SW Platforms. In: Kleinjohann, B., Kim, K.H., Kleinjohann, L., Rettberg, A. (eds) Design and Analysis of Distributed Embedded Systems. DIPES 2002. IFIP — The International Federation for Information Processing, vol 91. Springer, Boston, MA. https://doi.org/10.1007/978-0-387-35599-3_18
Download citation
DOI: https://doi.org/10.1007/978-0-387-35599-3_18
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-4937-3
Online ISBN: 978-0-387-35599-3
eBook Packages: Springer Book Archive