Book Volume 6225 2010

Cryptographic Hardware and Embedded Systems, CHES 2010

12th International Workshop, Santa Barbara, USA, August 17-20, 2010. Proceedings


ISBN: 978-3-642-15030-2 (Print) 978-3-642-15031-9 (Online)

Table of contents (30 chapters)

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  1. Front Matter

    Pages -

  2. Low Cost Cryptography

    1. Chapter

      Pages 1-15

      Quark: A Lightweight Hash

    2. Chapter

      Pages 16-32

      PRINTcipher: A Block Cipher for IC-Printing

    3. Chapter

      Pages 33-47

      Sponge-Based Pseudo-Random Number Generators

  3. Efficient Implementations I

    1. Chapter

      Pages 48-64

      A High Speed Coprocessor for Elliptic Curve Scalar Multiplications over \(\mathbb{F}_p\)

    2. Chapter

      Pages 65-79

      Co-Z Addition Formulæ and Binary Ladders on Elliptic Curves

    3. Chapter

      Pages 80-94

      Efficient Techniques for High-Speed Elliptic Curve Cryptography

  4. Side-Channel Attacks and Countermeasures I

    1. Chapter

      Pages 95-109

      Analysis and Improvement of the Random Delay Countermeasure of CHES 2009

    2. Chapter

      Pages 110-124

      New Results on Instruction Cache Attacks

    3. Chapter

      Pages 125-139

      Correlation-Enhanced Power Analysis Collision Attack

    4. Chapter

      Pages 140-157

      Side-Channel Analysis of Six SHA-3 Candidates

  5. Tamper Resistance and Hardware Trojans

    1. Chapter

      Pages 158-172

      Flash Memory ‘Bumping’ Attacks

    2. Chapter

      Pages 173-187

      Self-referencing: A Scalable Side-Channel Approach for Hardware Trojan Detection

    3. Chapter

      Pages 188-202

      When Failure Analysis Meets Side-Channel Attacks

  6. Efficient Implementations II

    1. Chapter

      Pages 203-218

      Fast Exhaustive Search for Polynomial Systems in \({\mathbb{F}_2}\)

    2. Chapter

      Pages 219-233

      256 Bit Standardized Crypto for 650 GE – GOST Revisited

    3. Chapter

      Pages 234-247

      Mixed Bases for Efficient Inversion in \({{\mathbb F}{((2^2)^2)}{2}}\) and Conversion Matrices of SubBytes of AES

  7. SHA-3

    1. Chapter

      Pages 248-263

      Developing a Hardware Evaluation Method for SHA-3 Candidates

    2. Chapter

      Pages 264-278

      Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs

    3. Chapter

      Pages 279-293

      Performance Analysis of the SHA-3 Candidates on Exotic Multi-core Architectures

    4. Chapter

      Pages 294-305

      XBX: eXternal Benchmarking eXtension for the SUPERCOP Crypto Benchmarking Framework

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