Chapter

Cryptographic Hardware and Embedded Systems, CHES 2010

Volume 6225 of the series Lecture Notes in Computer Science pp 248-263

Developing a Hardware Evaluation Method for SHA-3 Candidates

  • Luca HenzenAffiliated withLancaster UniversityIntegrated Systems Laboratory, ETH Zurich
  • , Pietro GendottiAffiliated withLancaster UniversityDepartment of Information Technology and Electrical Enginnering, ETH Zurich
  • , Patrice GuilletAffiliated withLancaster UniversityDepartment of Information Technology and Electrical Enginnering, ETH Zurich
  • , Enrico PargaetziAffiliated withLancaster UniversityDepartment of Information Technology and Electrical Enginnering, ETH Zurich
  • , Martin ZollerAffiliated withLancaster UniversityDepartment of Information Technology and Electrical Enginnering, ETH Zurich
  • , Frank K. GürkaynakAffiliated withCarnegie Mellon UniversityMicroelectronics Designs Center, ETH Zurich

Abstract

The U.S. National Institute of Standards and Technology encouraged the publication of works that investigate and evaluate the performances of the second round SHA-3 candidates. Besides the hardware characterization of the 14 candidate algorithms, the main goal of this paper is the description of a reliable methodology to efficiently characterize and compare VLSI circuits of cryptographic primitives. We took the opportunity to apply it on the ongoing SHA-3 competition. To this end, we implemented several architectures in a 90 nm CMOS technology, targeting high- and moderate-speed constraints separately. Thanks to this analysis, we were able to present a complete benchmark of the achieved post-layout results of the circuits.