Developing a Hardware Evaluation Method for SHA-3 Candidates

  • Luca Henzen
  • Pietro Gendotti
  • Patrice Guillet
  • Enrico Pargaetzi
  • Martin Zoller
  • Frank K. Gürkaynak
Conference paper

DOI: 10.1007/978-3-642-15031-9_17

Part of the Lecture Notes in Computer Science book series (LNCS, volume 6225)
Cite this paper as:
Henzen L., Gendotti P., Guillet P., Pargaetzi E., Zoller M., Gürkaynak F.K. (2010) Developing a Hardware Evaluation Method for SHA-3 Candidates. In: Mangard S., Standaert FX. (eds) Cryptographic Hardware and Embedded Systems, CHES 2010. CHES 2010. Lecture Notes in Computer Science, vol 6225. Springer, Berlin, Heidelberg

Abstract

The U.S. National Institute of Standards and Technology encouraged the publication of works that investigate and evaluate the performances of the second round SHA-3 candidates. Besides the hardware characterization of the 14 candidate algorithms, the main goal of this paper is the description of a reliable methodology to efficiently characterize and compare VLSI circuits of cryptographic primitives. We took the opportunity to apply it on the ongoing SHA-3 competition. To this end, we implemented several architectures in a 90 nm CMOS technology, targeting high- and moderate-speed constraints separately. Thanks to this analysis, we were able to present a complete benchmark of the achieved post-layout results of the circuits.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Luca Henzen
    • 1
  • Pietro Gendotti
    • 2
  • Patrice Guillet
    • 2
  • Enrico Pargaetzi
    • 2
  • Martin Zoller
    • 2
  • Frank K. Gürkaynak
    • 3
  1. 1.Integrated Systems LaboratoryETH Zurich 
  2. 2.Department of Information Technology and Electrical EnginneringETH Zurich 
  3. 3.Microelectronics Designs CenterETH Zurich 

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