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High-Speed Systolic VLSI Architecture for 2-D Forward Lifting-Based DWT

  • Research Article - Computer Engineering and Computer Science
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Abstract

In this paper, an efficient approach to design a 2-D systolic array for high-speed implementation of block-based lifting lossy 9/7 wavelet filter is proposed. The inherent advantage of the in place computation of the lifting-based discrete wavelet transform over the conventional convolution method makes it suitable for efficient hardware implementation with lower computational complexity. The row processor consists of processing elements arranged in a systolic manner, and for column processing, the lifting steps are computed concurrently, by mapping the coefficients to the same systolic arrays, using the cyclic symmetry property of the block of input image coefficients. The advantage of the discussed architecture is that it does not require additional memory for storing the intermediate coefficients. The functionality of the processing element in the systolic array improves the speed, by having the critical path delay of one multiplier and two adders computational time. The area efficient, high-speed design of the lifting algorithm is coded in hardware description language and implemented in Altera cyclone II field programmable gate arrays (FPGA). The implemented results show that the systolic architecture achieves a high speed of 260MHz with a lower accessing time of 0.246μs, when compared to other existing architectures, and reaches a speed performance suitable for real-time multimedia applications. This conceptual design of systolic arrays can be used as IP core in FPGA-based reconfigurable coprocessors.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Saveetha School of Engineering, Saveetha University, Chennai, 602105, Tamil Nadu, India

    N. Usha Bhanu

  2. Department of Electronics and Instrumentation Engineering, R.M.D.Engineering College, Anna University, Chennai, 601206, Tamil Nadu, India

    A. Chilambuchelvan

Authors
  1. N. Usha Bhanu
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  2. A. Chilambuchelvan
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Correspondence to N. Usha Bhanu.

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Usha Bhanu, N., Chilambuchelvan, A. High-Speed Systolic VLSI Architecture for 2-D Forward Lifting-Based DWT. Arab J Sci Eng 39, 6125–6135 (2014). https://doi.org/10.1007/s13369-014-1208-2

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  • DOI: https://doi.org/10.1007/s13369-014-1208-2

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