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An Efficient Architecture for Modified Lifting-Based Discrete Wavelet Transform

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Abstract

A high speed and memory efficient lifting based architecture for one-dimensional (1-D) and two-dimensional (2-D) discrete wavelet transform (DWT) is proposed in this paper. The lifting algorithm is modified in this work to achieve a critical path of one multiplier delay with minimum pipeline registers. A 1-D DWT structure with two-input/two-output and four-input/four-output is developed based on the modified lifting scheme. The proposed 2-D DWT architecture for the Daubechies 5/3 and 9/7 filter comprises of two 1-D processors, together with a transpose and a temporal memory. An efficient transpose block is presented, which utilizes three registers to transpose the output sequence of the 1-D DWT block. The transpose block is independent of the size of the image read for the transform. The scanning process of an \(N \times N\) image for a one-level 2-D transform is in Z fashion to minimize the temporal buffer to 4N and 2N for the 9/7 and 5/3 mode DWT respectively. The comparison results show that the proposed structure is hardware cost-effective and memory efficient, which is favorable for real-time visual operations. The model is described in VHDL and synthesized using the Cadence tool in 90 nm technology.

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Authors and Affiliations

  1. St Joseph Engineering College, Mangalore, Karnataka, India

    Rohan Pinto

  2. Manipal Institute of Technology, Manipal, Karnataka, India

    Kumara Shama

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  1. Rohan Pinto
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  2. Kumara Shama
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Pinto, R., Shama, K. An Efficient Architecture for Modified Lifting-Based Discrete Wavelet Transform. Sens Imaging 21, 53 (2020). https://doi.org/10.1007/s11220-020-00317-z

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