Microvias of 50 μm diameter in a Si chip were filled with Zn or Sn-Zn to form through-silicon vias by means of an electroplating/reflow process or a dipping method. In the case of the electroplating/reflow process, Zn was electroplated on a Cu seed layer in via holes, and a reflow was then performed to fill the via holes with the electroplated Zn. In the case of the dipping method, Zn via-filling and Sn-Zn via-filling were performed by dipping a via hole specimen into a molten bath of Zn or Sn-Zn. A filling pressure greater than 3 MPa during the via-filling is essential for ensuring that the via holes are completely filled with Zn or Sn-Zn and for preventing voids from being trapped in the vias. The melting temperature and electrical conductivity of the Sn-Zn alloys increases almost linearly with the content of Zn, implying that the thermal and electrical properties of the Sn-Zn vias can be easily controlled by varying the composition of the Sn-Zn vias. A chip-stack specimen was fabricated by flip-chip bonding of three chips with Zn vias.
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This work was supported by the Center for Electronic Packaging Materials (ERC) of MOST/KOSEF (Grant #R11-2000-085-08001-0).
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Jee, Y.K., Yu, J., Park, K.W. et al. Zinc and Tin-Zinc Via-Filling for the Formation of Through-Silicon Vias in a System-in-Package. J. Electron. Mater. 38, 685–690 (2009). https://doi.org/10.1007/s11664-008-0646-6
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DOI: https://doi.org/10.1007/s11664-008-0646-6