Skip to main content
Log in

The Scalability of Disjoint Data Structures on a New Hardware Transactional Memory System

  • Published:
International Journal of Parallel Programming Aims and scope Submit manuscript

Abstract

In this paper we present our experiences constructing and testing in-memory data structures designed to be disjoint enough for transactional memory to be profitable as a serialization mechanism with no fallback to traditional locking. Our goal was to restrict memory conflicts to actual contention situations so that transactional memory techniques could be used as efficiently as possible. We describe the hardware transactional execution facility in the IBM zEnterprise EC12 server. We present an order preserving hashed structure that permits insertion, deletion, and traversal operations typically supported by a sorted linked list. We also present a concurrent open addressing hash table structure. We measure the performance and scalability for these data structures on the IBM zEnterprise EC12 server. Our results show near linear scalability of the insertion and deletion operations for up to 96 CPUs. We also discuss transaction abort frequency and hardware/software interactions.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. Knight, T.: An architecture for mostly functional languages. In: Proceedings of the 1986 ACM LISP and Functional Programming Conference

  2. Herlihy, M., Moss, J.E.: Transactional memory: architectural support for lock-free data structures. In: Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, CA, May (1993)

  3. Shavit, N. Touitou, D.: Software transactional memory. In: Proceedings of the 14th Annual ACM Symposium on Principles of Distributed Computing, Ottawa, Ontario, August (1995)

  4. Herlihy, M., Luchangco, V., Moir, M., Scherer III, W.N.: Software transactional memory for dynamic-sized data structures. In: Proceedings of the 22nd Annual ACM Symposium on Principles of Distributed Computing, Boston, MA, July (2003)

  5. Saha, B., Adl-Tabatabai, A.R., Hudson, R.L., Minh, C.C., Hertzberg, B.: McRT-STM: a high performance software transactional memory system for a multi-core runtime. In: Proceedings of the 11th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, New York, NY, March (2006)

  6. Hammond, L., Wong, V., Chen, M., Carlstrom, B.D., Davis, J.D., Hertzberg, B., Prabhu, M.K., Wijaya, H., Kozyrakis, C., Olukotun, K.: Transactional memory coherence and consistency. In: Proceedings of the 31st Annual International Symposium on Computer Architecture, Munich, Germany, June (2004)

  7. Ananian, C.S., Asanovic, K., Kuszmaul, B.C., Leiserson, C.E., Lie, S.: Unbounded transactional memory. In: Proceedings of the 11th IEEE Symposium on High-Performance Computer Architecture, February (2005)

  8. Rajwar, R., Herlihy, M., Lai, K.: Virtualizing transactional memory. In: Proceedings of the 32nd Annual International Symposium on Computer Architecture, June (2005)

  9. Moore, K.E., Bobba, J., Moravan, M.J., Hill, M.D., Wood, D.A.: LogTM: Log-based transactional memory. In: Proceedings of the 12th Annual International Symposium on High Performance Computer Architecture, Austin, TX, February (2006)

  10. Damron, P., Fedorova, A., Lev, Y.: Hybrid transactional memory. In: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, October (2006)

  11. Kumar, S., Chu, M., Hughes, C.J., Kundu, P., Nguyen, A.: Hybrid transactional memory. In: Proceedings of the 11th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, New York, NY, March (2006)

  12. Minh, C.C., Trautmann, M., Chung, J.W., McDonald, A., Bronson, N., Casper, J., Kozyrakis, C., Olukotun, K.: An effective hybrid transactional memory system with strong isolation guarantees. In: Proceedings of the 34th Annual International Symposium on Computer Architecture, San Diego, CA, June (2007)

  13. Shriraman, A., Spear, M.F., Hossain, H., Marathe, V.J., Dwarkadas, S., Scott, M.L.: An integrated hardware-software approach to flexible transactional memory. In: Proceedings of the 34th Annual International Symposium on Computer Architecture, San Diego, CA, June (2007)

  14. Lev, Y., Moir, M., Nussbaum, D.: PhTM: phased transactional memory. In: Proceedings of the 2nd ACM SIGPLAN Workshop on Transactional Computing, Portland, OR, August (2007)

  15. Lev, Y., Maessen, J.-W.: Split hardware transactions: true nesting of transactions using best-effort hardware transactional memory. In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Salt Lake City, UT, February (2008)

  16. Yoo, R.M., Ni, Y., Welc, A., Saha, B., Adl-Tabatabai, A.-R., Lee, H.-H.S.: Kicking the tires of software transactional memory: Why the going gets tough. In: Proceedings of the 20th ACM Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, June (2008)

  17. Tremblay, M.: Transactional memory for a modern microprocessor. In: Keynote speech at 26th Annual ACM Symposium on Principles of Distributed Computing, Portland, OR, August (2007)

  18. Click, C.: Azul’s experiences with hardware transactional memory. Bay Area Workshop on Transactional Memory, January (2009)

  19. Haring, R., Ohmacht, M., Fox, T., Gschwind, M., Satterfield, D., Sugavanam, K., Coteus, P., Heidelberger, P., Blumrich, M., Wisniewski, R., Gara, A., Chiu, G.-T., Boyle, P., Chist, N., Kim, C.: The IBM blue gene/Q compute chip. IEEE Micro 32(2), 48–60 (2012)

  20. Intel Corporation: Intel Architecture Instruction Set Extensions Programming Reference. 319433-014, August (2012)

  21. IBM: IBM zEnterprise EC12 Technical Guide. SG24-8049-00, September (2012)

  22. Dice, D., Lev, Y., Moir, M., Nussbaum, D.: Early experience with a commercial hardware transactional memory implementation. In: Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, Washington, DC, March (2009)

  23. Wang, A., Gaudet, M., Wu, P., Amaral, J.N., Ohmacht, M., Barton, C., Silvera, R., Michael, M.: Evaluation of blue gene/Q hardware support for transactional memories. In: Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques, Minneapolis, MN, September (2012)

  24. Herlihy, M., Wing, J.M.: Linearizability: a correctness condition for concurrent objects. ACM Trans. Program. Lang. Syst. 12(3), 463–492 (June 1990)

  25. Guerraoui, R., Kapalka, M.: Opacity: a correctness condition for transactional memory. Technical Report LPD-REPORT-2007-004, EPFL, May (2007)

  26. Rajwar, R., Goodman, J.R.: Speculative lock elision: enabling highly concurrent multithreaded execution. In: Proceedings of the 34th International Symposium on Microarchitecture, Austin, TX, December (2001)

  27. Dragojevic, A., Herlihy, M., Lev, Y., Moir, M.: On the power of hardware transactional memory to simplify memory management. In: Proceedings of the 30th Annual ACM Symposium on Principles of Distributed Computing, San Jose, CA, June (2011)

  28. Jacobi, C., Slegel, T., Greiner, D.: Transactional memory architecture and implementation for IBM system z. In: Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, Vancouver, Canada, December (2012)

  29. IBM: z/Architecture Principles of Operation. SA22-7832-09, 10th edn (2012)

  30. Purcell, C., Harris, T.: Non-blocking hashtables with open addressing. Technical Report, University of Cambridge Computer Laboratory. UCAM-CL-TR-639, September (2005)

  31. Martin, D.R., Davis, R.C.: A scalable non-blocking concurrent hash table implementation with incremental rehashing. Unpublished manuscript, December 1997

  32. xxhash. https://code.google.com/p/xxhash/

  33. MurmurHash. http://en.wikipedia.org/wiki/MurmurHash

  34. Hash table. http://en.wikipedia.org/wiki/Hash_table

  35. Open addressing. http://en.wikipedia.org/wiki/Open_addressing

  36. Knuth, D.E.: The Art of Computer Programming, vol. 3, Addison-Wesley, Boston (1998)

Download references

Acknowledgments

The authors would like to thank their colleagues for valuable help in this work. Christian Jacobi provided many insights into the Transactional Execution Facility hardware in zEnterprise EC12. Maged Michael discussed issues related to disjoint data structures. Robin Tanenbaum was critical in wrangling the unreleased hardware so the authors could actually conduct the experiments.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Gong Su.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Su, G., Heisig, S. The Scalability of Disjoint Data Structures on a New Hardware Transactional Memory System. Int J Parallel Prog 43, 1192–1217 (2015). https://doi.org/10.1007/s10766-014-0322-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10766-014-0322-9

Keywords

Navigation