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A highly linear open-loop high-speed CMOS sample-and-hold

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Abstract

This paper presents an open loop high speed CMOS sample and hold with improved linearity. Previously, an open-loop S/H and a method of charge injection cancellation were introduced (Hadidi et al. in The 2006 International Conference on Solid State Devices and Materials 604–605, 2006). However, it requires many clock phases. In this paper a new charge injection cancellation scheme and switch linearization method is introduced. The proposed S/H could be implemented in a simple manner in contrast with the previous one while its linearity has been improved (especially in near nyquist frequencies). The proposed S/H with sampling rate of 500 MS/s achieves SNDR of 76 dB at nyquist single-tone input signal and SNDR of 72.5 dB at near nyquist dual-tone input signal. The sample and hold is implemented using TSMC 0.35 μm dual-poly quadruplet metal CMOS technology.

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References

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Authors and Affiliations

  1. Micro-electronics Research Lab, Urmia University, Urmia, Iran

    Morteza Mousazadeh

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  1. Morteza Mousazadeh
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Correspondence to Morteza Mousazadeh.

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Mousazadeh, M. A highly linear open-loop high-speed CMOS sample-and-hold. Analog Integr Circ Sig Process 90, 703–710 (2017). https://doi.org/10.1007/s10470-016-0912-0

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  • DOI: https://doi.org/10.1007/s10470-016-0912-0

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