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Interleaving with coroutines: a systematic and practical approach to hide memory latency in index joins

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Abstract

Index joins present a case of pointer-chasing code that causes data cache misses. In principle, we can hide these cache misses by overlapping them with computation: The lookups involved in an index join are parallel tasks whose execution can be interleaved, so that, when a cache miss occurs in one task, the processor executes independent instructions from another one. Yet, the literature provides no concrete performance model for such interleaved execution and, more importantly, production systems still waste processor cycles on cache misses because (a) hardware and compiler limitations prohibit automatic task interleaving and (b) existing techniques that involve the programmer produce unmaintainable code and are thus avoided in practice. In this paper, we address these shortcomings: we model interleaved execution explaining how to estimate the speedup of any interleaving technique, and we propose interleaving with coroutines, i.e., functions that suspend their execution for later resumption. We deploy coroutines on index joins running in SAP HANA and show that interleaving with coroutines performs like other state-of-the-art techniques, retains close resemblance to the original code, and supports both interleaved and non-interleaved execution in the same implementation. Thus, we establish the first systematic and practical approach for interleaving index joins of any type.

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Notes

  1. Retrieved from a profiling session of 60 s.

  2. We have not yet investigated how to form a pipeline with variable size, so we do not provide a corresponding SPP version.

  3. http://www.boost.org/doc/libs.

  4. https://en.wikipedia.org/wiki/Duff%27s_device.

  5. At the time of writing, Visual C++ and Clang are the only compilers that implement the technical specification for coroutines.

  6. An interested reader can find more information about C++ coroutines in the technical specification [6] and at Lewis Baker’s excellent blog: https://lewissbaker.github.io/.

  7. The observed speedups differ from the expected ones mainly due to rounding; group sizes cannot be floats.

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Authors and Affiliations

  1. School of Computer and Communication Sciences, École Polytechnique Fédérale de Lausanne, Lausanne, VD, Switzerland

    Georgios Psaropoulos & Anastasia Ailamaki

  2. SAP SE, Walldorf, BW, Germany

    Georgios Psaropoulos, Thomas Legler & Norman May

  3. RAW Labs SA, Lausanne, VD, Switzerland

    Anastasia Ailamaki

Authors
  1. Georgios Psaropoulos
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  2. Thomas Legler
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  3. Norman May
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  4. Anastasia Ailamaki
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Correspondence to Georgios Psaropoulos.

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Psaropoulos, G., Legler, T., May, N. et al. Interleaving with coroutines: a systematic and practical approach to hide memory latency in index joins. The VLDB Journal 28, 451–471 (2019). https://doi.org/10.1007/s00778-018-0533-6

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