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Efficient inter-core power and thermal balancing for multicore processors

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Abstract

Nowadays the market is dominated by processor architectures that employ multiple cores per chip. These architectures have different behavior depending on the applications running on the processor (parallel, multiprogrammed, sequential), but all happen to meet what is called the power and temperature wall. For future technologies (less than 22 nm) and a fixed die size, it is still uncertain the percentage of processor that can be simultaneously powered on. Power saving and power budget mechanisms can be useful to precisely control the amount of power been dissipated by the processor. After an initial analysis we discover that legacy power saving techniques work properly for matching a power budget in thread-independent and multi-programmed workloads, but not in parallel workloads. When running parallel shared-memory applications sacrificing some performance in a single core (thread) in order to be more energy-efficient can unintentionally delay the rest of cores (threads) due to synchronization points (locks/barriers), having a negative impact on global performance. In order to solve this problem we propose power token balancing (PTB) aimed at accurately matching an external power constraint by balancing the power consumed among the different cores. Experimental results show that PTB matches more accurately a predefined power budget (50 % of the original peak power) than other mechanisms like DVFS. The total energy consumed over the budget is reduced to only 8 % for a 16-core CMP with only a 3 % energy increase (overhead). We also introduce a novel mechanism named “Nitro”. Nitro will overclock the core that enters a critical section (delimited by locks) in order to free the lock as soon as possible. Experimental results have shown that Nitro is able to reduce the execution time of lock-intensive applications in more than 4 % by overclocking the frequency by 15 % in selected program phases over a period of time that represents a 22 % of the total execution time. We conclude the work with an analysis of the thermal effects of PTB in different CMP configurations using realistic power numbers and heatsink/fan configurations. Results show how PTB not only balances temperature between the different cores, reducing temperature gradient and increasing signal reliability, but also allows a reduction of 28–30 % of both average and peak temperatures for the studied benchmarks when a peak power budget of 50 % is exceeded.

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Notes

  1. The difference between maximum and minimum die temperatures in a given time.

  2. These spare tokens represent the amount of power that the core can dissipate and still be under the power budget, will be defined in Sect. 3.2.

  3. Group of instructions delimited by branches.

  4. Reorder Buffer.

  5. As mentioned before, we can store information about past power behavior at a basic block level to predict future power trends and increase power matching accuracy.

  6. We only report results for a 50 % power budget due to space limitations for the sake of visibility. For less restrictive power budgets PTB also works properly.

  7. DVFS and DFS are applied at a core-level to increase its accuracy when matching the power budget.

    Fig. 8
    figure 8

    Normalized energy (top) and AoPB (bottom) for a varying number of cores and PTB policies

    Full size image

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Acknowledgments

This work was supported by the Spanish MEC, MICINN and EU Commission FEDER funds under Grants CSD2006-00046 and TIN2009-14475-C04. Also by the EU-FP7 ICT Project “Embedded Reconfigurable Architecture (ERA)”, contract No. 249059.

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Authors and Affiliations

  1. Department of Computer Architecture, University of Murcia, Murcia, Spain

    Juan M. Cebrián, Daniel Sánchez & Juan L. Aragón

  2. Department of Information Technology, University of Uppsala, Uppsala, Sweden

    Stefanos Kaxiras

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  1. Juan M. Cebrián
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  2. Daniel Sánchez
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  3. Juan L. Aragón
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Correspondence to Juan M. Cebrián.

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Cebrián, J.M., Sánchez, D., Aragón, J.L. et al. Efficient inter-core power and thermal balancing for multicore processors. Computing 95, 537–566 (2013). https://doi.org/10.1007/s00607-012-0236-6

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