Abstract
A wideband low-noise transconductance amplifier (LNTA) with high linearity is proposed. The differential LNTA adopts complementary common-gate (CG), current mirror (CM) and common-source (CS) schemes to obtain noise and distortion cancellation, and \(g_{m}\)-enhancement. A high third-order input intercept point (IIP3) is obtained due to the distortion cancellation and the complementary characteristics of NMOS and PMOS transistors. The gain expansion of the class-AB CS stage compensates the gain compression of the CG–CM stage, which leads to a high large-signal linearity. A wide input matching bandwidth is achieved by utilizing a \(\uppi \)-type input matching network without the use of on-chip bulky inductors, and the passive voltage gain of the \(\uppi \)-network further enhances the effective transconductance. Designed in a 0.18-\(\upmu \hbox {m}\) CMOS process, the simulation results show that it provides a minimum noise figure (NF) of 2.95 dB and a maximum transconductance of 79 mS from 0.1 to 3.6 GHz. An input 1-dB compression/desensitization point and an IIP3 of 8.1/5.59 and 18.14 dBm are obtained, respectively. The NF is degraded by 0.3 dB with a 0-dBm blocker. The circuit draws 10.7 mA from a 2.5-V supply, and the core area is only \(0.5 \times 0.12\,\hbox {mm}^{2}\).
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Appendix Volterra Series Analysis
Appendix Volterra Series Analysis
To capture high-frequency effect, Volterra series analysis is performed as below. Referring to Fig. 8 and repeating (9)–(10) for \(V_{x}\) and \(V_{1}\),
Applying Kirchhoff’s current law at each node of the circuit in Fig. 8, the following equations can be obtained:
where \(Z_x (s)=\frac{1}{sC_x }\), \(Z_1 (s)=R_1 \left\| {\frac{1}{sC_1 }} \right. \), and \(Z_{a}\) is given in (8). \(g_{m1} \), \({g}'_{m1} \) and \({g}''_{m1} \) are given in (1).
To find the linear transfer functions \(A_1(s)\) and \(B_1 (s)\), we excite the circuit with a single tone \(v=e^{st}\). Substituting (12) and (13) in (14) and (15), equating the coefficients of \(e^{st}\) on both sides of (14) and (15), and solving for \(A_1 (s)\) and \(B_1 (s)\), we get
where
To find the second-order term \(A_2 (s_1 ,s_2 )\) and \(B_2 (s_1 ,s_2 )\), we excite the circuit with two tones \(v=e^{s_1 t}+e^{s_2 t}\). Substituting (12) and (13) in (14) and (15), equating the coefficients of \(e^{(s_1 +s_2 )t}\) on both sides of (14) and (15), and solving for \(A_2 (s_1 ,s_2 )\) and \(B_2 (s_1 ,s_2 )\), we get
Likewise, \(A_3 (s_1 ,s_2 ,s_3 )\) and \(B_3 (s_1 ,s_2 ,s_3 )\) are given by
where
For the common-source stage and current mirror output stage, the parasitic capacitances and output impedances of \(M_{2}\) and \(M_{4}\) can be ignored since the load resistance \(R_\mathrm{L}\) is small enough, and the memoryless Taylor series is applied to reduce the analysis complexity. The output current can be expressed as
where \(g_{m2} \), \(g_{m4} \), \({g}'_{m2} \), \({g}'_{m4} \), \({g}''_{m2}\) and \({g}''_{m4} \) are given in (1).
Plugging in the above Volterra kernel expressions, the fundamental and third-order output current \(i_{o}\) expressions are found to be
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Chen, J., Guo, B., Zhang, B. et al. A Highly Linear Wideband CMOS LNTA Employing Noise/Distortion Cancellation and Gain Compensation. Circuits Syst Signal Process 36, 474–494 (2017). https://doi.org/10.1007/s00034-016-0320-9
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DOI: https://doi.org/10.1007/s00034-016-0320-9