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Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits

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Abstract

Reduction in leakage power consumption is one of the important issues in the field of VLSI. Numerous techniques have been proposed by several researchers, based on threshold voltage variations and gate modifications. In this paper, a novel pass transistor-based pull-up/pull-down insertion technique is proposed to minimize standby leakage. Experimental results on various ISCAS’89 benchmark circuits show that proposed technique has an improvement up to 20, 36 and 33 % on average in leakage reduction, delay improvement and area savings respectively, compared to the transmission gate-based technique. All benchmark circuits are simulated using H-spice Tool with an 180-nm standard cell library based on BSIM3 transistor model. Finally, the efficacy of the proposed approach in improving various metrics has been compared with present state-of-art methods.

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Authors and Affiliations

  1. Department of ECE, G.V.P. College of Engineering (Autonomous), Visakhapatnam, India

    V. Leela Rani

  2. Department of ECE, JNTUH College of Engineering, Hyderabad, India

    M. Madhavi Latha

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  1. V. Leela Rani
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  2. M. Madhavi Latha
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Correspondence to V. Leela Rani.

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Leela Rani, V., Madhavi Latha, M. Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits. Circuits Syst Signal Process 35, 4139–4152 (2016). https://doi.org/10.1007/s00034-016-0257-z

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  • DOI: https://doi.org/10.1007/s00034-016-0257-z

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